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tags: FPGA Embedded Design
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# Verilog 基本語法

[Final Project](https://hackmd.io/W71dbrJXQBGgOPFJDidWFw)
[現代處理器設計：原理和關鍵特徵](http://hackfoldr.org/cpu/https%253A%252F%252Fhackmd.io%252Fs%252FHk2CscGcl)
## Verilog 常用語法
### Verilog 基礎模組架構(Module Architecture)
* Modules
* A module is the basic building block in Verilog
* Every module starts with the keyword module, has a name, and ends with the keyword endmodule
* A module can be
* A design block
* A simulation block, i.e., a testbench
* Examples:

        module add_a (...);
        ...
        endmodule

* Module Ports
* Module ports describe the input and output terminals of a module
* List in parentheses after the module name
* Declared to be `input`, `output`, or `inout`(bi-direction)
* Examples

        module add/*Module Name*/(sum, a, b, carry_in, carry_out)//Module ports 
        output sum, carry_out; // declaration of port modes
        input a, b, carry_in;  // declaration of port modes
        ...
        endmodule

* Full Adder and Nested Module
* Combinational Logic Gates: `and`, `nand`, `or`, `nor`, `xor`, `nxor`, `buf`, `not`
* Example:

        module Add_full(sum, carry_out, a, b, carry_in); // parent module
            input a, b, carry_in;
            output carry_out, sum;
            wire w1, w2, w3; // declare a wire
            Add_half M1(w1, w2, a, b);
            Add_half M2(sum, w3, w1, carry_in);
            or(carry_out, w2, w3);
        endmodule
    

### Verilog 資料型態
* Nets "wire": structural connectivity
* Examples:

    wire b, c; // declare two wire
    wire a = b & c; // declare two wire and assign the value
    wire d = 1'b0; // initialize the value with 0

* Registers "reg": abstraction of storage(may or may not be physical storage)
* Reference: [verilog 基本宣告](https://ithelp.ithome.com.tw/articles/10191542)
* 暫存的功能和變數很像，可以直接給定一個數值，主要的功能在於保持住電路中的某個值，部戲像接線(wire)被驅動才能改變它的內涵值
* wire和reg的敘述
* vectors
* arrays
* Both nets and registers are informally called signals and may be wither scalar or vector

### Verilog 時間控制(Timing Control)
* 事件：
* 當一條接線或是暫存的值被改變
* 接收新的值
* 用來觸發一個或多個敘述
* `@`: 正規事件控制(Regular Event Control)，
* 當信號產生正緣(posedge)、負緣(negedge)、轉換(transition)或這值被改變時敘述才會被執行
* `always`:
* 一般always @ (*) 是指裡面的語句是組合邏輯(Combinational Logic) 的。
* 代替了敏感變量。而一般時序邏輯 (Sequential Logic) 要寫成

          always @ (posedge clk or negedge rst) 
          //時鐘信號clk上升沿或者復位信號rst下降沿的時候執行always塊內的程式碼。

### Verilog 電路合成語法
* 運算子
### Verilog 常用敘述
verilog 中，給職的方法有三種：
* =
* <=
* assign: 給值

### Verilog 模組(Module)

module 模組名稱(input ..., output ...)
    wire, wand, wor, reg, ....
    assign ...
    always ...
    begin
        // Usage of Task and function
    end
    // declare task and function
endmodule

* Example:
* 4 Bits Ripple Carry Adder

### Verilog `parameter`

### Verilog 數值表示
Reference: [Verilog 数值表示](https://www.runoob.com/w3cnote/verilog-number.html)
* Verilog signal values
* 0: logical 0, FALSE
* 1: logical 1, TRUE
* x: an unknown value
* z: a high impedence condition
* Verilog 整數數值表示法
* 總共四種
* 十進位('d or 'D)
* 十六進位('h or 'H)
* 二進位('b or 'B)
* 八進位('o or 'O)
* 符號前面的數值表示bit數

****
Reference:
* [Verilog基礎教程](https://www.runoob.com/w3cnote/verilog-tutorial.html)
* [Verilog進階教程](https://www.runoob.com/w3cnote/verilog2-tutorial.html)