---
# System prepended metadata

title: 數位電路實驗暨 verilog 學習（四）iverilog installation
tags: [verilog, 數位邏輯電路練習]

---

# 數位電路實驗暨 verilog 學習（四）
> 本章改為使用iverilog 進行測試,這是由於verilator專注於單cycle及logic的正確度測試,這搞的要使用時序化simulation的情況下有夠瞎雞巴複雜
> 參考自 [Installing Icarus Verilog and GTKWave on Ubuntu for Verilog Simulation](https://medium.com/@0xYori/installing-icarus-verilog-and-gtkwave-on-ubuntu-for-verilog-simulation-d6d31eee2096)
## iverilog 安裝
```
sudo apt update
```
```
sudo apt install iverilog
```
```
sudo apt install gtkwave
```
## Testing
> Test mux21
```
module multiplexer_2_1(
  input a,
  input b,
  input select,
  output y
);

assign y = (select)?b:a;
endmodule
```
> Testing bench
```
`timescale 1ns/100ps  // time scale  : (單位時間)/（精度）
module multiplexer_2_1_tb;

 //inputs
 reg a, b, select;
 //outputs
 wire y;

// 實例化MUX
 multiplexer_2_1 u0_DUT(
  .a(a),
  .b(b),
  .select(select),
  .y(y)
 );

 //initialize inputs

 initial begin
//simulation files dumped to the test_2_1mux file
  $dumpfile("test_2_1mux.vcd");
  $dumpvars;
  
  a=1'b0;
  b=1'b0; 
  //選a 
  select=1'b0;
  // # + (delay 秒數)
  #5 a=1'b1; //a -> 1
  
  //10ns時選b
  #5 select = 1'b1; 
  
  #5 b=1'b1;
  #5 a=1'b0;
  #5 $finish;
 end
endmodule
```
> 產生波形檔
```
 $dumpfile("test_2_1mux.vcd");
 $dumpvars;
```
> 運行
```
iverilog -o mux_wave_2_1(自訂輸出檔檔名) multiplexer_2_1.v(測試的module) multiplexer_tb_2_1.v(test bench file)
```
```
vvp mux_wave_2_1
```
```
gtkwave test_2_1mux.vcd
```
> 以上結束 下回回到clk和reg的實做 [實驗五](https://hackmd.io/@1p0_VOUHTXGcHlBU9A0OEA/BJ9pGdahC)