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# System prepended metadata

title: HDL
tags: [book]

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---
tags: book
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HDL
===
logic design
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- multiplier
    - [signed multiplier & radix-4 signed multiplier](/8zZi1bKYRgW8k8NK2sPpqA)

verilog
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- verilog
    - __
- testbench
    - [tb模擬結果調色](/4tEmhnIWSNWLwRxYaOj9Fg)
- system verilog

UVM
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- cocotb

Algorithm
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- quantization
- arithmetic
- codic
- systolic array
- fifo
- linebuffer
- pipeline/parallel/folding/unfolding

Q&A
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1. assign vs always case if-else: [連結](https://iter01.com/615779.html)
2. python verilog verification
    - [DIP project - sobel](/cebx-NwLSia1xtHGSm9fPw) 
    - [data format](/mcB_P6qFQF6Cg6SigoqDXA)