# :wolf: Logic Design 2020

###### tags: `verilog` `digital design` `邏輯設計` `邏設` `數位邏輯設計`

[TOC]

## Something You Have to Know.

<font color=#878787>This website contains verliog tutorials and lab infomations.
Please read the tutorials before you start the labs.

以下是這學期關於 Verilog 的教材和課堂守則，請各位在寫 Lab 之前，先把下面的介紹看完，相信在做 Lab 時，會更加流暢。 </font>

## Course Rules

1. Discussion with your classmates is allowed, but do not share your code to other studens😡.

2. If you have any question, feel free to open a discussion on ILMS.

3. Copy (or plagiarizing) is not allowed. You will get 0 point in this course.
---
1. 同學可以互相討論作業，<font color=#bb3033>但嚴禁共享 Code</font>
3. 問題盡量在<font color=#bb3033> ilms 討論區上發問與討論</font>

5. 凡是抓到抄襲，<font color=#bb3033>抄襲者及被抄襲者皆當掉</font>

<!-- ## Info

<font color = #bf2222>3/19 Add tutorials
3/5 Create the website.

</font>
-->
<!-- <font color = #878787>4/16 新增 Finite Statehttps://hackmd.io/s/ByKQJmePN Machine
4/16 新增 nWave
4/16 更新 testbench
3/28 新增 lab2
3/27 新增 Makefile
3/27 新增 Synthesis GUI - Design Vision
3/27 新增 Design Vision _ Synthesis circuits
3/9 新增 工作站手把手教學
3/9 新增 testbench 介紹
3/7 新增 lab1
3/6 新增 ! 跟 ~ 的差別
3/6 新增 描述電路的三種方法
3/6 新增 什麼是 always block
3/6 新增 i++ 與 i = i+1
3/6 新增 程式碼的執行順序
2/18 建立此教材 -->

</font>

## Lab Review
- [AS4 part2 Verilog Practice Review](https://hackmd.io/@dppa1008/Logic_Design_As4_Review)
- [Lab3 Finite State Machine Review](/bpvTZCfYSbGmjo4Nfq0t0Q)

## Lab

- [Lab 1 Basic Verilog](https://hackmd.io/@dppa1008/Logic_Design_Mak_Lab1)
- [AS4 part2 Verilog Practice](/KDemPr4UQTaVHx7_-JwEhA)
- [Lab 3 Finite State Machine](/tr3Ps-qQSZSVIzpTemhu1w)

<!-- >* [Lab1 Kevin number detector](https://hackmd.io/s/ryMp4D9IN)
>* [Lab2 ALU](https://hackmd.io/s/Sk39CSvO4)
>* [Lab3 Path Sum](https://hackmd.io/s/rJPhjjl54)
>* [Lab4 Queue](https://hackmd.io/s/S1SQMpSsN)
-->

## Verilog Skills
>* [Fundamentation of Verilog](https://hackmd.io/s/SyBpQWQOG)
>* [Wire v.s. Reg](https://hackmd.io/s/SkG8-fmuf)
>* [Other Data Types](https://hackmd.io/s/BJhsVGQuz)
>* [Difference between " ! " and " ~ "](https://hackmd.io/s/BkjYrFHOG)
>* ["Hello World" in verilog](https://hackmd.io/s/BJWS5_B_G)
>* [什麼是 always block](https://hackmd.io/s/Sy2UHbVYG)
>* [i++ 與 i = i+1](https://hackmd.io/s/SJ5n_WNKf)
>* [程式碼的執行順序](https://hackmd.io/s/rkWdqZ4tz)
>* [testbench 介紹](https://hackmd.io/s/HkwfhzevV)
>* [Finite State Machine](https://hackmd.io/ntyIA5KbSIK3eJTqGSwDYA)

## Tool

> <font>WorkStation </font>
>
>* [How to enter a server - Windows](https://hackmd.io/s/Skn_2Az_M)
>* [How to enter a server - Mac](https://hackmd.io/s/H1pQWJmdG)
>* [Upload/download files to/from a server - Windows](https://hackmd.io/s/r16Z8yXOz)
>* [Upload/download files to/from a server - Mac](https://hackmd.io/s/HkBWDJ7Of)
>* [Introduction to linux commands](https://hackmd.io/s/SkK19lQdG)
>* [Synthesis GUI - Design Vision](https://hackmd.io/s/HycSafRYf)
>* [Makefile](https://hackmd.io/s/B1HF7jRtG)
>* [nWave](https://hackmd.io/s/Bkso7ImcV)

## Resource

> - [Verilog HDL 教學講義](https://hom-wang.gitbooks.io/verilog-hdl/content/)
> - [asic-world](http://www.asic-world.com/)