Logic Design 2020

tags: verilog digital design 邏輯設計 邏設 數位邏輯設計

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  • Something You Have to Know.
  • Course Rules
  • Lab Review
  • Lab
  • Verilog Skills
  • Tool
  • Resource

Something You Have to Know.

This website contains verliog tutorials and lab infomations.
Please read the tutorials before you start the labs.

以下是這學期關於 Verilog 的教材和課堂守則，請各位在寫 Lab 之前，先把下面的介紹看完，相信在做 Lab 時，會更加流暢。

Course Rules

1. Discussion with your classmates is allowed, but do not share your code to other studens😡.

2. If you have any question, feel free to open a discussion on ILMS.

3. Copy (or plagiarizing) is not allowed. You will get 0 point in this course.

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1. 同學可以互相討論作業，但嚴禁共享 Code

2. 問題盡量在 ilms 討論區上發問與討論

3. 凡是抓到抄襲，抄襲者及被抄襲者皆當掉

Lab Review

• AS4 part2 Verilog Practice Review
• Lab3 Finite State Machine Review

Lab

• Lab 1 Basic Verilog
• AS4 part2 Verilog Practice
• Lab 3 Finite State Machine

Verilog Skills

• Fundamentation of Verilog
• Wire v.s. Reg
• Other Data Types
• Difference between " ! " and " ~ "
• "Hello World" in verilog
• 什麼是 always block
• i++ 與 i = i+1
• 程式碼的執行順序
• testbench 介紹
• Finite State Machine

Tool

WorkStation

• How to enter a server - Windows
• How to enter a server - Mac
• Upload/download files to/from a server - Windows
• Upload/download files to/from a server - Mac
• Introduction to linux commands
• Synthesis GUI - Design Vision
• Makefile
• nWave

Resource

• Verilog HDL 教學講義
• asic-world