# :sunflower: :hatched_chick: Happy Verilog :pig: :baseball:
> [color=#b80909]
> * CS210201 Logic Design
>
> * 以下是這學期關於 Verilog HDL 的輔助說明教材，希望同學對每個章節詳細閱讀，課程內容將依照上課進度持續更新連結。

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## __注意事項__
>* [x]同學可以互相討論作業，<font color=#bb3033>但嚴禁共享 Code</font> [color=#bb3033]
>* [x]TA time <font color=#bb3033> 固定在星期一晚上 19:00~21:00 </font> [color=#bb3033]
>* [x]問題盡量在<font color=#bb3033> ilms 討論區上發問與討論</font> [color=#bb3033]
>* [x]作業 <font color=#bb3033>不接受補交、不會延期 </font> [color=#bb3033]
>* [x]TA time <font color=#bb3033>不會延長 </font> [color=#bb3033]
>* [ ]待補充 ..
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## Lab
>[color=#c9666b]
>* [Lab1 Fibonacci number detector](https://hackmd.io/s/rydbOnSYx)
>* [Lab2 ALU](https://hackmd.io/s/rJ48LtL5l)
>* [Lab3 Vector Inner Product Unit](https://hackmd.io/s/ryjZEGd3g)
>* [Lab4 Data Encryption Standard](https://hackmd.io/s/BJtL5Wc6x)
>* [Lab5 Image Processing Filters](https://hackmd.io/s/HJCFzsrg-)
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## Verilog HDL 基本介紹
>[color=#b56568]
>* [Verilog HDL 撰寫前置作業](https://hackmd.io/s/rJfaeVADx)
>* [Module Architecture](https://hackmd.io/s/SyZKQ1jdx)
>* [Data Types](https://hackmd.io/s/SkB2CR6Oe)
>* [描述電路的三種層次](https://hackmd.io/s/HJkRifete)
> * Structure Description at Gate Level
> * Dataflow Description
> * Behavior Description
>* [Module Connection](https://hackmd.io/s/ryk3FvkYg)
>* [Lexical Conventions](https://hackmd.io/s/r1v7PDeYl)
>* [多工器 Mux 常用的描述方法](https://hackmd.io/s/BJVFuFZYe)
>* Sequential circuit
> * [Blocking & Non-Blocking 介紹](https://hackmd.io/s/B1AHou-Fx)
>* [Testbench](https://hackmd.io/s/BJHfnf7Kl)
>* [Circuits 範例](https://hackmd.io/s/H1lFtSgYg)
>* [FAQ](https://hackmd.io/s/rJ9As11Kl)

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## Tool
>[color=#d8b2bf]
>* Workstation
> * [如何從個人電腦連線到工作站](https://hackmd.io/s/SJ88DVJYl)
> * [如何下載/上傳工作站上的檔案](https://hackmd.io/s/Sk9qyNyYx)
> * [工作站基本介紹](https://hackmd.io/s/SJDy_J1Yx)
>* [Makefile](https://hackmd.io/s/HyL4R4lYe)
>* [Synthesis GUI - Design Vision](https://hackmd.io/s/BJfK9MKcl)
>* [nWave](https://hackmd.io/s/rJB_1B7tx)

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## 其他線上教學資源
>[color=#e3c9d6]
>* [asic-world](http://www.asic-world.com/)
> * 裡面含有豐富的範例資源，但請同學們要特別注意哪些是可以合成的語法，哪些是不能合成的語法。
>
>* [Verilog HDL 教學講義](https://hom-wang.gitbooks.io/verilog-hdl/content/)
>
>* [Verilog 基礎 - 陳鍾誠的網站](http://ccckmit.wikidot.com/ve:main)

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