---
# System prepended metadata

title: 積體電路設計實驗_Final Project

---

* # 積體電路設計實驗_Final Project

## Github link
https://github.com/reggiehsu111/ECC

## Block Diagram
![](https://i.imgur.com/NKEls4X.png)






## Module
```verilog=
module Top();
    input i_rst;
    input i_clk;
    input [3:0] a;
    input [3:0] prime;
    input [3:0] Px;
    input [3:0] Py;
    input [3:0] k;
    
    output [3:0] kP;

endmodule

module Control();
    input i_rst;
    input i_clk;
    input GFAU_done;
    input PartKey;
    input [31:0] GFAU_result; // Result from GFAU
    input [31:0] x1, y1, x2, y2;
    
    output [31:0] Px_mont, Py_mont; // To GFAU
    output [1:0] operation_select;
    output done_keyshift;
    output done_control;
endmodule

module KeyShift();
    input i_rst;
    input i_clk;
    input shift;
    input done;
    input [31:0] key;
    output PartKey;
    
endmodule

module GFAU();
    input i_rst;
    input i_clk;
    input [31:0] Px_mont. Py_mont;
    input [1:0] operation_select; // 00, 01, 10, 11 add, subtract, multiple, divide
    output done;
    output[31:0] Px_mont_out, Py_mont_out;
endmodule

module lookup();
endmodule

module Domain_Transfer();
    input i_rst;
    input i_clk;
    input [31:0] Px, Py;              
    input clk, reset, ToMont;   // To Montgomery Domain
    output [31:0] Px_mont, Py_mont;
    output done;
endmodule

module Arithetic_function();
    input i_rst;
    input i_clk;
    input bit_of_key;
    output double_or_add;   
    output done_control
endmodule


```


## Computation Count

### MontMult

- 2n

### MontDiv
- 3n

### Point Add
- 2 MontMult
- 1 MontDiv
- Total: O(7n)

### Point Double
- 3 MontMult
- 1 MontDiv
- Total: O(9n)