---
# System prepended metadata

title: GPC3

---

# GPC3
## Previous Note
 #->Constant
 
 $->Hexadecimal


## Introduction

## Memory Mapping
### 1.Summary:

![](https://i.imgur.com/I1e5KXH.png)

(a).first 48k bytes(0000H~BFFFH):Common bank=>can access directly
(b).0800h-083fh:Interrupt Vector
用來判斷中斷的種類(External,Internal ,Software )

### 2.ROM
(a)addressing area 64k,beyond 64k must be addressed by mapping.

### 3.ROM Bank Control Register
(a)bank size=16k bytes,P_Bank is 00H~FFH,addressing to 4M Bytes.
(b)000H~01FFH:access data in ROM and Control Register.
(c)0200H~07FFH:Trigger illegal address reset.

### **

---
**4.RAM:3 Types
    
    256byte:80h~17FH
    128byte:80h~FFH
    96bytes:A0h~FFh
    
    
## Register

A(8):Arithmetic or logical operation.
X(8):memory buffer,offset,counter.
Y(8):as stated above.
PC(16)
SP(8)
P(8):usually offer result of previous instruction executed.

## Addressing Mode
**1.Immediate**
EX: LDA #79

(a).2 bytes of machine language code, 1 for the instruction and 1 for the number.

(b).we cannot specify a number larger than 255

**2.Absolute**
EX: LDA 315

3 bytes of machine language code, since this instruction must be able to load the accumulator from anywhere in memory. That is, to code for any address above 255 requires 2 bytes, and we also need 1 byte for the instruction

**3.Absolute Indexed** 
EX:LDA $0342,X

if x=3

loads the accumulator from memory location $0345, since $0342 + 3 = $0345

(a) are applicable to any address in the computer, not just zero page addresses. 

(b)are both 3-byte instructions. They each require 4 machine cycles to execute

**4.Zero page**

EX: LDA 45

used to load the accumulator from an address in the first 256 bytes of memory, page zero. 

**5.Zero page indexed**

EX: LDA $43,x

if x=5

load the accumulator from the hexadecimal address $43 + 5, or $48.

(a)only 2 bytes when converted to machine language and requires 4 machine cycles to execute

**6.Accumulator**

**7.Indexed indirect**

EX:LDA ($43,X)

![](https://i.imgur.com/KUZFiXL.png)

We add the contents of the X register to the base address specified and obtain $43 + 4 = $47. We then look in memory locations $47 and $48, and interpret the 2 bytes there as a new address, $E453 (remember, low byte first and then high byte). Finally, we execute the instruction, loading the accumulator from memory location $E453. This operation requires 6 machine cycles and is therefore the slowest instruction we have yet encountered. Since it requires zero page addressing, it needs only 2 bytes per instruction. As was mentioned above, this instruction is seldom used. Its primary use is for establishing a table on page zero and then accessing this table to provide addresses elsewhere in memory. However, your ATARI has limited zero page space available for your use, especially when either the BASIC or Assembler/Editor cartridge is in place; we generally don't have room to construct such a table on page zero, and we use other addressing modes to construct such tables elsewhere. This mode can be used, however, in applications not designed for use with a cartridge. Arcade-type games are one example: the game stands alone, and you are relatively free to use more of page zero for your own use.

**8.Indirect**

EX:JUMP ($31FE)

**9.Indirect indexed**

EX:LDA ($43),Y

![](https://i.imgur.com/PE0HBXr.png)

The 6502 first looks at memory locations $43 and $44 and takes the values stored there as an address. In this example, it finds the values ＃＄53 and ＃＄E4, and, since it knows the first byte is the low value of the address, and the second is the high value, it realizes that the address referred to is $E453. The 6502 then adds the offset value, 6, obtained from the Y register, to this address, and calculates the address to be accessed to be $E453 + 6 = $E459. Finally, it executes the LDA instruction, and loads the accumulator from memory location $E459.

 

**9.Relative**

## Instruction Sets

BCC (Branch on Carry Clear)

BNE (Branch on Not Equal to Zero)

RTS (Return from Subroutine)

PHA (Push the Accumulator onto the Stack)

RTI (Return from Interrupt)





## I/O Configuration

1.valid I/O varies in each GPC3 body.
![](https://i.imgur.com/bfA3c7V.png)

2.Two registers is used to change the I/O status,Direction and Buffer registers.

![](https://i.imgur.com/yH7KWp0.png)

Note:
1.	I/O’s initial state: input floating.
2.	When I/O is a wakeup source, it must be input mode.
3.	When entering into sleep mode, all I/O are not allowed to be floating state. Otherwise, extra current drain may be existed.	If IO is a wakeup source, I/O data port must be latched before entering into sleep mode.
4.	The pull-low resistor will be switched to 1MΩ automatically to **reduce power consumption** when the input state is high.


*floating input:
An unconnected input to a gate, because it floats at the threshold voltage for the device.
輸出Output或輸入Input腳位因為空接，導致無可預期的結果出現，就會讓你的電路或程式出現莫名其妙的輸出甚至當機

一定要串接一個電阻到Vcc或是GND，我們稱為Pull High或Pull Low。

switch 斷開時 logic gate 會讀到低電位，接上後是高電位。所以高電位表示邏輯 1，低電位表示邏輯 0。

![](https://i.imgur.com/qILJvXL.png)



#### Example
Set IOA[7:6] as input floating, IOA [5:4] as input pull low, IOA [3:2] as output low and IOA [1:0] as output high

LDA #%00110011
STA P_IOA_Buffer
LDA #%00001111  //1=output
STA P_IOA_Dir


## I/O structure

![](https://i.imgur.com/3d9mBl6.png)

Since the IOs are set as input pull low, when each key is pressed, the pull low resistance will be set high impedance (1MΩ) to save power.

## I/O Control Registers

1.Direction Register

2.Data Register

Written :
P_IOA_DATA(W)=P_IOA_BUFFER(W)

Reading :
P_IOA_Data(R) = I/O pad state !=P_IOA_Data(W)


3.IOA Direction Register

4.IOA Data Register

5.IOA Buffer Register

6.IOB Direction Register

7.IOB Data Register

8.IOB Buffer Register

## I/O Special Functions

### 1. IR Transmitter 紅外線發射器
產生方波

![](https://i.imgur.com/d66mM9O.png)

 IOA[7] is able to generate IR waveform
 
 activate IR output, IOA[7] must be set output  mode
 
 TimerA setting determines the IR frequency. IOA[7] must be set output mode to make IR signal transmitted to IOA[7]
 
 ![](https://i.imgur.com/hxEYdjc.png)

#### EX:
LDA STA LDA
STA	#B1H
P_TMA_DataL #0FH
P_TMA_DataH_Ctrl
LDA AND STA LDA ORA STA LDA ORA	P_IOA_Buffer #01111111B
P_IOA_Buffer P_IOA_Dir #10000000B
P_IOA_Dir P_MISC #00000100B
AND STA	#11111100B P_MISC

### 2. IR Control Register

![](https://i.imgur.com/HpyWGBG.png)


The clock source of IR signal comes from TimerA timeout. The P_IOA_Dir[7] determines whether or not the IR signal is transmitted to IOA[7]. Furthermore, P_IOA_Buffer[7] determines the IOA[7] outputs either in non-inverted output or inverted output.

![](https://i.imgur.com/YJMtprI.png)
![](https://i.imgur.com/BxSdNil.png)

*scalar:純量輸出
clipper:截波

*Duty Cycle:在一個信號週期裡，代表1的正脈衝的持續時間與脈衝總周期的比值

EX:The following program is used to generate one 38KHz and 1/2 duty IR output with 6MHz system clock.   To get 38KHz, 1/2 duty IR output, the Timer A should be set with 76KHz
![](https://i.imgur.com/KMe8RSt.png)


 ### 3.RTC(Real Time Clock)
 
 是負責記錄時間的元件，出現在需要長期使用時鐘的電子設備中。例如學校定時關閉冷氣的裝置，以及手機上的鬧鈴功能。
 
2 source type: 2Hz or 8Hz

an external 32768Hz crystal and two capacitors  are required

#### RTC Control Register

![](https://i.imgur.com/ObvNMps.png)


Note:
1.	When P_MISC[3] is set “1”, no matter what the IOB[5:4] status is, hardware will automatically set the IOB[5:4] to 32768Hz crystal mode and user does not need to set up IOB[5:4].
2.	To use RTC function, IOB[5:4] must connect with a 32768Hz crystal. If only P_MISC[3] is set ”1” and no external 32768Hz crystal is added, this function is void.
3.	To use RTC as wakeup source, set the P_MISC[3] to “1” before entering sleep mode.

EX:A 32768Hz crystal normally requires longer start-up time (over 200ms, even longer at lower voltage). If you only set P_MISC[3] to “1” whenever using RTC, it needs to wait for the start-up time before normal operating. Therefore, we recommend user setting P_MISC[3] to “1” at power on; before activate RTC interrupt, set this bit to “0” (clear RTC counter) and set back to “1” immediately. This will precisely command the 1st interrupt; otherwise, the 1st interrupt occurrence may take place differently based on the voltage change
 
 ![](https://i.imgur.com/FZqvsI3.png)

## 4. PWM I/O
 four I/Os to generate 256-level pulse width

### I/O Control Register

![](https://i.imgur.com/aap1kTG.png)
![](https://i.imgur.com/TNcQ0Vu.png)


### PWM I/O 0 Duty Control Register

corresponds to the **IOB[0]**. To output PWM pulse from IOB[0],  IOB[0] must be set output  mode (P_IOB_Dir[0] = 1).

EX:
Suppose PWM clock source is FCPU /4; PWM I/O 0 outputs to IOB[0] and duty is 32/256; PWM I/O 1 outputs to IOB[1] and duty is 64/256

![](https://i.imgur.com/tkZzg6H.png)




## External Interrupt

1.**IOA0** can also be an external interrupt source or wakeup source

2.this pin must be set **input mode**.

3.we can further set the **P_INT_Ctrl2 [0]** to rising edge triggered or falling  edge triggered for the interrupt.

*Rising Edge-Triggered上升邊緣(正緣)觸發:
 如果輸出變化對時脈輸入從0到1轉換有反應，稱此
正反器被時脈的上升邊緣觸發。
 Falling Edge-Triggered下降邊緣(負緣)觸發:
 如果輸出變化只對時脈輸入從1到0的轉換有反應，
稱此正反器被時脈的下降邊緣觸發

![](https://i.imgur.com/WeorEfw.png)

*TB:選擇Clock 時脈


EX:
Suppose IOA0 is set an external interrupt source with rising edge triggered. After the setting is settled, IOA0 level changes from low to high and it will trigger the external interrupt. Further, CPU will jump to V_IRQ_EXT to execute interrupt subroutine.

![](https://i.imgur.com/B8uskF9.png)
![](https://i.imgur.com/JvP0qV5.png)


*Ctrl1:p39

## Feedback

將一個放大器的輸出電壓的一部份，經由適當的網路送
回該放大器之輸入端，稱為回授(feedback)。


1.**IOA.1** pin is for Feedback **Output** pin & **IOA.2** pin is used for Feedback **Input** pin.

2. In RC Mode, its Feedback output CLK cycle varies much more in which the CLK cycle T is about 1* RC @ 4.5V. Moreover, the voltage and R resistor will influence the CLK cycle. We recommend R=1M ohm or above.

3.When Feedback is a **wakeup source**, it only supports **RC mode**

4. In RC Mode, IOA.2 is capable of waking up system in a fixed time period 


EX:
![](https://i.imgur.com/8sQEOOF.png)

5.Wake up Source
(a)	**RC Mode**: It uses RC OSC to generate change of IO status and further to trigger key-change.**IOA.2** is capable of waking up system in a fixed time period

(b)**X’TAL Mode**: Under Sleep mode, because Feedback X’TAL CLK stops, it cannot be a wakeup source.

6.TMA Clock Source

(a)	When IOA.1 is used for a Feedback TMA EXT CLK Source, CLK generated by Feedback will be inputted to TMA and similar to TMA EXT Input, it uses P_TMA_DataH_Ctrl[6:4] for frequency division. Input ing Feedback CLK to TMA, P_TMA_DataH_Ctrl[6:4] must set ”100 ~ 111” (Timer A clock source uses External CLK)

EX:

## Key Change Interrupt/Wake up

IO ports can be used as key change interrupt source or wakeup source via configuring **P_KeyWakeUpSel ($0C)**

## High Sink Current I/O

*Sink current 與 Source current 一個很簡單的判斷方式為 "依電流方向判斷" 。若電流方向為流入 MCU 則稱為 sink current 灌電流(如灌水一般；中國大陸用語) ；若電流方向為從 MCU 流出則為 source current 拉電流(中國大陸用語)。


When **IOB[3:0]** (total of 4 I/Os) are set output low mode, the sink current will be two times higher than other I/Os 

## Timer A External Clock Source

1.use IOA1
2.TimerA is an up-counter. When clock source is an external clock, it will detect IOA1 status. When IOA1 generates a rising-edge signal, TimerA will be incremented by 1. When TimerA overflows, it generates an interrupt signal.

## Interrupt

two type

1.IRQ(Interrupt Request)*8

2.NMI(Non-Mask Interrupt Request):only Timer A *1

硬體中斷的一類，無法通過在中斷封鎖暫存器中設定位遮罩來關閉。典型例子是時鐘中斷（一個硬體時鐘以恆定頻率—如50Hz—發出的中斷）。
priority: TimerA, TimerB, TimerC, TB1, TB2, RTC, KEY, and External Interrupt.

### Interrupt Control Register - 1
![](https://i.imgur.com/v7ZStgG.png)

?TB:固定時間,比Timer慢

### Interrupt Control Register - 2
![](https://i.imgur.com/y9fHInV.png)

### Interrupt Status - 1
![](https://i.imgur.com/KzYJejf.png)

write 1 to clear
### Interrupt Status - 2
![](https://i.imgur.com/UJVZWM8.png)






## Timer/Counter

使用內部時脈稱為「計時器(Timer)」，因為單晶片的內部 clock 相當準確，可做為計
算時間的依據；若使用外部時脈則稱為「計數器(Counter)」，因外部訊號不見得固定
時間，累加結果就不具有時間上的意義，只能表示發生的次數。

three 12-bit up-count timers/counters, Timer A, Timer B and Timer C.

![](https://i.imgur.com/fzIvtzG.png)


### 1.Timer A


#### Timer A Data Low Byte Register
![](https://i.imgur.com/tzUJO6M.png)

#### Timer A Data High Byte and Control Register
![](https://i.imgur.com/UHKYO0H.png)

Tone Mode
Speech Mode 

人聲/單調?

### 2.Timer B
Low Byte:
![](https://i.imgur.com/bNjNTQR.png)

High Byte and Control:
![](https://i.imgur.com/SdA2lPt.png)

### 3.Timer C

While writing P_TMC_DataL(14H), it will not change content in Timer C Data
Only when writing **P_TMC_DataH_Ctrl(11H)**, it changes the 12-bit Timer C Data.

 Data Low Byte Register:
 ![](https://i.imgur.com/vYWqGbt.png)

 
 Data High Byte and Control Register:
 ![](https://i.imgur.com/auwpV2S.png)

 4.
Formula:
**N=4096-[F(TMR)/F(S)]**


Note:
N = 12-bit timer data
FS = Frequency requested from user FTMR = Timer frequency

EX:
Set TimerA source as “FCPU/4” and generate a 12KHz interrupt with 6 MHz FCPU. FCPU = 6000000
FTMR = FCPU /4 = 1500000 FS = 12000
N = 4096 – (1500000 / 12000) = B1EH

![](https://i.imgur.com/DYRpZkl.png)



## Sleep/Wake up

1.enter sleep mode.  First, set up the wakeup source and then **write 5AH  to P_Sleep (0EH)**. If no wakeup source is activated, even 5AH is written into P_Sleep(0EH),If contents other than 5AH is written into P_Sleep(0EH), it will cause CPU **reset**.

2.All IO ports are opted to key change interrupt source or wakeup source via manipulating P_KeyWakeUpSel ($0C)

3. When I/O is a wakeup source,to avoid noise causing CPU wakeup abnormal, the setting of P_MISC(1DH)Key change wakeup/interrupt should be defined a port as a whole.

![](https://i.imgur.com/8PSvL0B.png)

*General Purpose Input/Output (GPIO)
a generic pin on an integrated circuit whose behavior, including whether it is an input or output pin, can be controlled by the user at run time
GPIO 是種具有彈性且可以藉由軟體控制 (software-controlled) 的數位訊號

### Key Change Wake Up/Interrupt Selection and RTC Selection Register

1.be determined as key change interrupt source or wakeup source via **P_KeyWakeUpSel ($0C).**

2.`P_INT_Ctrl1[1](19H)` must be set “1” (key change interrupt enable)

3.before entering sleep mode, it must be **latch I/O** state in order to detect whether I/O state is changed. To latch I/O, read its data register (01H, 04H, 07H or 0A). **P_KeyWakeUpSel [3] ($0C)** determines whether IOB[5:4] is a GPIO or RTC pin. If RTC is activated, this bit must set to “RTC pin” as well as setting P_MISC(1DH)’s bit3 to “1”.

4.When **`P_KeyWakeUpSel [2:0]($0C)`** is used to control Feedback function, to activate Feedback function, P_KeyWakeUpSel [0] bit must set ”1”. In addition, P_KeyWakeUpSel [1] bit can configure  IOA.2  feedback input pin whether or not to be a wakeup/ interrupt source.  And, P_KeyWakeUpSel [0] bit can  set IOA[2:1] for feedback RC mode or X’TAL mode.

![](https://i.imgur.com/oon1mzf.png)

### Wakeup De-glitch(脈衝干擾) Setting Register

Purpose:
To prevent CPU from incorrectly triggered by noise which may cause CPU wakeup function failure from sleep mode

Way:
if its IO signal is less than the de-glitch width in **P_MISC(1DH) bit[7:6]** , the signal will be treated as a noise and further to be filtered



![](https://i.imgur.com/kiIgKna.png)

### Sleep Register


EX:
Make sure all I/Os are NOT in floating state and have reached steady status before latch data. Any floating state may cause high standby current drain at sleep mode. Disable de-glitch function (P_MISC[7:6] = 00) before latch I/O status and enable it when enter sleep mode.

![](https://i.imgur.com/XkGbk1v.png)
![](https://i.imgur.com/0RIk4Cu.png)


## RESET

to prevent system from unexpected incorrect operation which may cause CPU crashed or inoperative

POR (Power On Auto Reset), LVR/LVD (Low Voltage Auto Reset/ Low Voltage Detect), WDT(Watchdog Timer, Mask Option) and illegal Address Reset. 
 
 ### Watchdog Reset
   If the watchdog is not cleared, CPU will assume the program is running in an abnormal condition and therefore, CPU will reset the system to the initial state and start running the program all over again.
  
  #### Clear Watchdog Counter Register
the watchdog should be cleared within every 1 second @ 8MHz, or 1.3 seconds @ 6MHz by writing #A5H to P_WatchdogClear(W)(0FH).
If not doing,the timer will generate a reset signal to reset system.
  
 
 ### LVD (LOW VOLTAGE DETECT)
 When voltage is **lower than 2.4+/-0.1V**, the P_INT_Status2 (1CH)’s bit 7 (LVD_Flag) is “1”,


### LVR (LOW VOLTAGE RESET)
 The system may be halt when power drops below VLVR, which is normally caused by battery-bouncing, heavy loading or low-battery condition. With the LVR function, a reset signal is generated to reset the system while the power drops **below VLVR**. Normally, the VLVR is around **2.0V**.

### Illegal Address Reset

When CPU directly accesses the addresses 0200H ~ 07FFH, it will trigger an illegal address reset.
 
 ## Audio Output
 
 1.The **$29H, $2BH, $2DH** corresponds  to  channel 1, channel 2, and channel 3’s highest 8 bits ([11:4]). The **$28H, $2AH, and $2CH**’s bit [7:4] corresponding to channel 1, channel2, and channel 3’s lowest 4 bits ([3:0])
 
2. **P_MISC(1DH)’s bit[5]** can   be selected as hardware mixing option.

**bit=1**=>
when data of these three channels summed over FFFH, it retains at FFFH.   If the summation is less than FFFH, it will be outputted to PWM output. 

**bit=0**=>
 scalar will be activated. When three channels add up over a specific value, the exceeding part will be multiplied by a weight which limit the summation exceeds FFFH.
 
  It prevents the volume away from boom and improves volume quality as well.
  
 3.GPC3 features a hardware volume control which can be configured by **P_MainVolumeCtrl (23H) ‘s bit[7:4]** to change PWM volume.


4.has a hardware tone generator. Each channel is able to playback **speech or tone music**. To playback a specific tone frequency, we need to set **P_TMx_High_Ctrl’s bit[7]** to “1” and set up the Timer Data to designated frequency. Timer A/B/C controls the tone generator of channel 1/2/3. The Tone  volume is determined by P_PWM_Data_CHxH (29H, 2BH, 2DH) and P_PWM_Data_CHxL (28H, 2AH, 2CH).


![](https://i.imgur.com/h8AjMMf.png)

### PWM Control Register

![](https://i.imgur.com/eUXW7ao.png)


### PWM Volume Control Register

differs unapparent, we recommend using the following seven levels: MainVolume[3:0] = 0H, 1H, 2H, 3H, 7H, 8H, FH.


### Channel 1 Data Low Byte Register


Each channel resolution is 12-bit; The higher 8-bit data of Channel 1 is stored at P_CH1_Data_H(29H) and the lower 4-bit data is stored at P_CH1_Data_L [7:4] (28H)

....

P25
p32
TB1,TB2? P39

