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# System prepended metadata

title: CHERI HLS

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# CHERI HLS Road Map for FPGA 2024

- [ ] Play with CHERI-enabled RISC-V
    - [x] Jianyi gets a basic matrixmult kernel with AXI interface
    - [x] Peter gets Flute running in the cheri-hls repo
    - [ ] Jianyi & Peter gets Flute running with the HLS IP (bare metal)
- [ ] Connecting it with HLS
    - [ ] Connecting HLS kernels with Flute core with virtual address
    - [ ] Adding more hardware components to model different user processes
    - [ ] Adding hardware components that enables capability on shared DDR
- [ ] Enable capability on the HLS kernels to access DDR memory
    - [ ] Paul build a FreeBSD driver for run-time memory allocation
    - [ ] Sync with Flute on physical addresses
- [ ] Run experiments on a few benchmarks (multi-threaded programs)
    - [ ] fft
    - [ ] histogram
    - [ ] los
    - [ ] matrixadd
    - [ ] matrixmult
    - [ ] matrixtrans
    - [ ] sparse_matrixmult
    - [ ] substring
- [ ] Question: What if HLS kernels share memory?
- [ ] Security evaluation: soundness or completeness?

### Meeting today

- [x] Vitual Address Story?
- [x] Physical Address Story?
- [x] Paper Results?
- [ ] Work to reach there?


- [ ] Each pointer has a cap from HLS compiler (passing to driver)
- [ ] associate lookup
- [ ] tabular cap
- [ ] in-memory
- [ ] IOMMU

