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# System prepended metadata

title: OpenSMART vs OpenPiton

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# OpenSMART vs OpenPiton 

## Interconnect differences: 
1.
OP : cluster based multi-chip architecture/configuration, inter chip and intra chip NoC
OS: mutli-core single chip architecture based NoC

2. 
OP: provides support for hardware acclerator like FPU in a tile
OS: hardware accelerator can be placed on a different node, as a separate IP

3. Topology: 
OP: three NoC routers to support three 2D NoCs
OS: single 2D mesh NoC

4. 
OP: supports point to point ordering to ensure no protocol level deadlock happens. 
OS: doesn't support ordered network. But, a VNET with 1 VC is always ordered (single/mutli-flit)

5. Flow control: 
OP: no virtual channels and wormhole XY routing(single buffer at input port)
OS: supports multiple virtual channels, thus virtual channel XY routing(multiple buffers at input port)

6. 
OP: doesn't support SMART mechanism
OS: supports SMART link bypass mechanishm

7. 
OP: supports multi-flit packet for a fixed custom cache coherence protocol.
OS: agnostic of cache coherence protocol, multi-flit implementation is WIP. 

8.
OP: Each  hop  takes  one  cycle  when  packets  are going straight and one extra cycle for route calculation when a packet must make a turn at a switch. Not 
OS: The latency of router can be configured. Default supports 1 & 2 cycle router and can be further pipelined. Link traversal takes 1 cycle and router supports look ahead routing.

9. 
OP: The L2 needs to be placed together with core on a tile
OS: We have configurability to distribute L2 but can be placed together with core or on a separate node.




