---
# System prepended metadata

title: 'SOC: Lab4-2 report'

---

## SOC: Lab4 report


<!-- 
JJbest
![Screenshot from 2025-04-28 02-15-40](https://hackmd.io/_uploads/rksQa93Jee.png)
![Screenshot from 2025-04-28 02-23-16](https://hackmd.io/_uploads/Bkf-ys3ygg.png)

```
LA Test 1 started
FIR Test 1 started
FIR Test 1 passed, Latency = 103075 ns
FIR Test 2 started
FIR Test 2 passed, Latency = 103075 ns
FIR Test 3 started
FIR Test 3 passed, Latency = 103075 ns
Total Latency = 309225 ns
LA Test 2 passed

```
clock period =25ns

103075 / 25 = 4123 cycle
4123 cycle / 64 data = 64cyle/per data



![Screenshot from 2025-05-06 03-56-49](https://hackmd.io/_uploads/SJXyWBPgxg.png)
 
 
 
 

![螢幕擷取畫面 2025-05-13 175612](https://hackmd.io/_uploads/ryYrhsgWxe.png)
51500 / 25 = 2060 cycle



49925 / 25 = 1997 cycle

![image](https://hackmd.io/_uploads/B1ePiJzZee.png)
33125 / 25 = 1325 cycle -->
## Overview
Optimization sequence:464->126->64->25->16->13->12
#### fir_control.c (without O3) (464cyle)
```C=
for (int i=0; i<64; i++) {
    while ((reg_fir_control >> 4) & 1 != 1) {} // wait until reg_fir_x (0x00 [4]) is ready
    reg_fir_x = i;
    while ((reg_fir_control >> 5) & 1 != 1) {} // wait until reg_fir_y (0x00 [5]) is ready
    outputsignal[i] = reg_fir_y;
}
```

#### fir_control.c (no loop edition) (without O3 :126cyle   O3:64cyle)
```C=
reg_fir_x = 0;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[0] = reg_fir_y;

// i = 1
// while ((reg_fir_control >> 4) & 1 != 1) {}
reg_fir_x = 1;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[1] = reg_fir_y;

// i = 2
// while ((reg_fir_control >> 4) & 1 != 1) {}
reg_fir_x = 2;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[2] = reg_fir_y;

// i = 3
// while ((reg_fir_control >> 4) & 1 != 1) {}
reg_fir_x = 3;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[3] = reg_fir_y;

........

// i = 62
// while ((reg_fir_control >> 4) & 1 != 1) {}
reg_fir_x = 62;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[62] = reg_fir_y;

// i = 63
// while ((reg_fir_control >> 4) & 1 != 1) {}
reg_fir_x = 63;
// while ((reg_fir_control >> 5) & 1 != 1) {}
outputsignal[63] = reg_fir_y;
```
clock period =25ns

103075 / 25 = 4123 cycle
4123 cycle / 64 data = 64cyle/per data

without O3 :126cyle/per data




## Optimization process
#### fir_control.c
```C=
uint32_t i;
reg_fir_x = 0;
for (i = 1; i < 64; i++) {
    outputsignal[i] = reg_fir_y;
    reg_fir_x = i;
}
outputsignal[i] = reg_fir_y;
```


### Cycle 25(O3 and instruction reorder)
![image](https://hackmd.io/_uploads/By3Ms_vbel.png)



```C=
uint32_t i;
reg_fir_x = 0;
for (i = 1; i < 64; i++) {
    outputsignal[i] = reg_fir_y;
    reg_fir_x = i;
}
outputsignal[i] = reg_fir_y;
```
### Cycle 16(O3 and instruction reorder)
![image](https://hackmd.io/_uploads/B1Og5dPbel.png)
**fir.v modified**
Pipe receiving x data, operation: mul and add, sending y data
### Cycle 13
![image](https://hackmd.io/_uploads/B1n4tOwbgx.png)

**fir_control.c modified**
Send two x data in the begining, latter, repeatly receive y and send x.
```C=
uint32_t i;
    i = 0;
    reg_fir_x = 0;
    reg_fir_x = 1;
    while(i <= 61)
    {
        outputsignal[i] = reg_fir_y;
        i++;
        reg_fir_x = i+1;
    }
    outputsignal[62] = reg_fir_y;
    outputsignal[63] = reg_fir_y;
```
**.out modified** 
![image](https://hackmd.io/_uploads/SkdLCdvZlg.png)
![image](https://hackmd.io/_uploads/BJxHuCYZxl.png)

**fir.v modified**
Add input buffer after SS bus, output buffer before SM bus
### Cycle 12
![image](https://hackmd.io/_uploads/Hk0no9FZgx.png)

**fir.v modified**
Decouple valid and ready: `sm_tvalid` is only associated with `y_buffer`; `ss_tready` is only associated with `x_buffer`
