--- # System prepended metadata title: Software Architecture of 8088 and 8086 microprocessors tags: [微算機與組合語言] --- --- tags : 微算機與組合語言 --- ###### 國立臺北大學資工系江宥旻 Software Architecture of 8088 and 8086 microprocessors === Micro architecture of the 8086/8088 microprocessor --- 內部接腳 ![8088-8086](https://i.imgur.com/CroBGyD.png =500x) 匯流排 BUS + 位址匯流排 Address BUS + $A_0 \sim A_{19}$，共20條線 + CPU透過位址匯流排指定所要存取的記憶體。 + 位址匯流排的信號由CPU發出，故具有**單向性**。只能由CPU來指定記憶體位址，無法由記憶體來指定CPU位址。 + 資料匯流排 Data BUS + $D_0 \sim D_7(D_{15})$ + CPU與Memory之間，透過資料匯流排來傳遞資料。 + 資料匯流排內的資料信號是**雙向性**的，CPU和Memory之間可以互相傳遞資料。 + 8088有8條，能夠一次存取8位元的資料 + 8086有16條，能夠一次存取16位元的資料 + 控制匯流排 Control BUS + 其他接腳 + CPU透過控制匯流排來告訴外部裝置現在要執行什麼動作。 > 基本上是CPU告知外面的元件，CPU正要做什麼 + 由CPU發出控制信號控制各裝置，所以控制匯流排的信號具有**單向性**。 + 擷取指令 + CPU會透過位址滙流排先送出指令位址 (CS：IP） + CPU會透過控制滙流排送出指令讀取的訊號 + 記憶體送出所要讀取的指令到資料滙流排，CPU就將資料滙流排的資料讀入 + CPU儲存資料到Memory + CPU會透過位址滙流排先送出位址(DS：SI(DI)) + CPU會透過資料滙流排送出資料 + CPU會送出寫入的訊號，告訴記憶現在要寫入 ![cpu-bus](https://i.imgur.com/2XKBmf4.png =300x) --- + Internal architecture + BIU (Bus Interface Unit) + Fetch Instructions from memory + Read/Write data from/to Memory/Ports + Performing external bus operations + Fetch instruction and data + EU (Execution Unit) + Decoding the fetched instruction by BIU + Execution of the decoded instruction + Instruction Pipeline + `Instruction queue` + `Parallel processing` ![](https://i.imgur.com/ep3hu2Q.png =300x) ![](https://i.imgur.com/WB3mwr4.png =300x) --- **指令週期** + 擷取指令 Fetch Instruction **(Memory)** + 解碼 Decoding **(CPU)** + 擷取資料 Retrieve Data **(Memory)** + 執行 Execution **(CPU)** + 存回結果 Store Result(Write Back) **(Memory)** **F** D **R** E **S**   第一個指令  **F** D **R** E **S**  第二個指令   **F** D **R** E **S**     **F** D **R** E **S** :::info **平行處理 Parallel processing** 由於每個步驟都是由CPU和Memory分工合作，當第一個指令在Decoding時，第二個指令可以Fetch Instruction ::: --- + BIU prefetch instructions into instruction queue + Registers + segment + pointer + data + ALU + Arithmetic logic unit + Flags + Status + Control ![BIU_EU](https://i.imgur.com/o4uWwXr.png =500x) Software Model of the 8086/8088 microprocessor --- 記憶體1MBytes + Register：16bits + 80286以上：32bits + Instruction Pointer + Segment Register + CS (Code Segment) + DS (Data Segment) + ES (Extra Segment) + SS (Stack Segment) + Data Register + AX + BX + CX + DX + Pointer & Index Register + BP (Base Pointer) + SP (Stack Pointer) + SI (Source Index) + DI (Destination Index) + Status Register (Flags) + 共有14個暫存器 ![register](https://i.imgur.com/fyIRJXb.jpg =500x) --- Instruction Pointer指到CPU`下一個要讀取`的指令位址，方便CPU去讀取下一個指令，`會自動增加`。 Segment Register是指到該區段`一開始的位址` :::info 每一個程式，內部都可以分成三個區域 + 程式區、資料區和堆疊區 + 利用區段暫存器來儲存這些區域的開始位址 ::: Data register：資料暫存器是暫時儲存資料的地方 AX：Accumulator累積器，CPU內部執行運算時資料儲存的主要位址 BX：Base Register CX：Count Register ```cpp for (i = 0; i < n; i++) ``` DX：Data 全部都是16bits(2Bytes)的暫存器，例如AX：AH，AL (High，Low) | AH | AL | |:------:|:------:| | 8 bits | 8 bits | 可擴展(Extend)為32bits，EAX、EBX、ECX和EDX Pointer & Index Register 指標搭配索引暫存器 + CS：IP **程式區** + DS：SI **來源資料區** + ES：DI **目的資料區** + SS：SP(BP) **堆疊區** 實際位址：$CS * 16 + IP$ Ex. CS：IP = 0100H：0010H => 實際位址：0100**0**H + 0010H = 01011H > 若是16進制，則CS後面加一個0 > 若是2進制，則CS後面加四個0 Status Register (Flags) 狀態暫存器 (旗標) + PSW(Process Status Word) + 每一個指令執行後的狀態 + 經常邏輯判斷的依據 + 利用一些狀態暫存器來顯示一些指令執行的狀態，以便後續的判斷 --- 8088 supports `1MBytes` of external memory > 00000H ~ FFFFFH Data stored in the memory + Even(odd)-address boundary + 若資料的大小是n倍數，則它被存放的位址就是n的倍數開始 ![](https://i.imgur.com/GrOObUd.png =400x) ![](https://i.imgur.com/7u1VVKf.png =200x) Memory address space and data organization --- + Big-endian + Motorola CPU + 最高位元存在最低的位址 + ![](https://i.imgur.com/Bku0QwV.png =300x) + Little-endian (8086/8088) + Intel CPU + 最低位元存在最低的位址 + ![](https://i.imgur.com/Lw9PbJw.png =300x) + Aligend word + A word of data stored at an even-address boundary + Misaligned + Aligend Double word + Located at an address that is a multiple of 4 [關於記憶體對齊(Alignment)](http://opass.logdown.com/posts/743054-about-memory-alignment) ![mas](https://i.imgur.com/SUJRlrl.png =300x) Data Types --- Data types + Char：8bits + Integer：16(32)bits + Long：32(64)bits > 1Nibble = 4bits > 1Byte = 8bits Signed and Unsigned IEEE 754 BCD ASCII + A = 41H + a = 61H + 0 = 30H Segment register and memory segmentaiotn --- Memory are partitioned into segments (64K in 8088) + Each is assigned a base address that identify its starting address + CS：code segment + DS：data segment + SS：stack segmnt + ES：extra segment ![segment](https://i.imgur.com/wC3IVFC.jpg =300x) > 指到開始的地方，目的端、來源端，則有兩塊記憶體 Dedicated, reserved, and general-use memory --- There are some location are dedicated or reserved for particular used + 00H~7FH for store the address of ISR(Interrupt service routine) + 不管什麼CPU都有資源中斷 + 外接的裝置都有一個ISR，例如Keyboard輸入時，就是一個ISR + 80H~FFFEFH：opened and general-use + FFFF0H~FFFFBH：hardware reset jump instruction + FFFFC~FFFFFH：power on jump instruction ![](https://i.imgur.com/eUHKOm6.jpg =300x) :::info CS：IP預設一開始就會指到JMP JMP，電腦開機時，馬上跳到BIOS，執行完BIOS才會啟動OS ::: Instruction Pointer --- 所有的記憶體位址都使用一個區段暫存器和一個指針暫存器來`定址(找資料)` + Code area are located using CS:IP to organize a 20-bits address for identifying whole 1Mbytes space + Both CS and IP are 16 bits wide + One segment still is 64Kbytes(原因是CS不動情形下, IP只有16Bits, 只有216個位置) + CS：code base + IP：offset + $CS * 16 + IP$ 得到20Bits的位址(實體位址) + Each process has its own CS & IP 值 + IP will increase the value automatically after fetched an instruction to point to next instruction(會自動++) ![CS-IP](https://i.imgur.com/MJFPl98.jpg =200x) > IP永遠指到下一個指令的位址 ### 記憶體位址 + $CS * 16 + IP$ + $DS * 16 + SI$ + $ES * 16 + DI$ + $SS * 16 + SP$ 記憶體位址，若CS：IP是二進制，則CS加四個0。 ![CS-IP_address](https://i.imgur.com/CG2goXQ.jpg =400x) 透過CPU的$A_0 \sim A_{19}$的位址線(位址滙流排)送出去給記憶體，要求要讀取記憶體中的指令。 Data register --- Four general-purpose data registers (儲存資料的暫存器) > Can be used as the source or destination of an operand during an arithmetic operation + AX(AH，AL) + Accumulator + BX(BH，BL) + Base + CX(CH，CL) + Count that usually used for loop instruction + DX(DH，DL) + Data :::success **低階指令**： ```asm MOV AX, 1234h ``` 指令(運算子) 目的運算元, 來源運算元 > CPU運算：+ - * / AND OR NOT ::: :::success Example： + MOV AX, 1234h + ADD AX, BX + AX <- AX + BX + AND AL, 02H + AL <- AL & 02H + MOV CL, AH + CL <- AH + MOV DH, 24d ::: > EAX, EBX, ECX, EDX for 32bits microprocessor Pointer and index register --- Two pointer registers and two index registers + They store what are called offset address + SP & BP for stack segment + SI & DI for data and extra segment + SI：offset for source operand + DI：offset for destination operand ![pointer-index](https://i.imgur.com/qNmedeM.jpg =300x) Status register --- Also called **flags register** Are able to use these flags to alter the sequence in which the program us executed, for instance, a jump to another part of the program + JZ：jump on zero + JC：jump on carry-out ![status-register](https://i.imgur.com/5iv5MXs.jpg =400x) | Flag | 說明 | |-----------|----------| | Carry | 進位，借位 | | Parity | 同位 | | Auxiliary | 輔助進位 | | Zero | 零 | | Sign | 符號 | | Overflow | 溢位 | + Status Flags + CF + 進(借)位 + PF + 資料檢查，偶同位 + AF + nibble的進(借)位，BCD + ZF + 結果是否為0 + SF + 看是正還是負 + OF + 是否有溢位 + Control flags (CPU控制) + TF + If TF is set, 8088 goes into the single-step mode (逐步執行的意思啦！) + Very useful for debugging programs (除錯用) + IF (中斷) + 接腳在NMI(none-maskable interrupt) + For the 8088 to recognize maskable interrupt requests at its interrupt (INT) input, the IF must be set + When IF is reset, requests at INT are ignored and the maskable interrupt interface is disabled + 每一個中斷都有一對應的中斷服務常式Interrupt Service Routine(ISR) + DF (決定方向的) + Determine the direction in which string operations will occur + When set(1), the string instruction automatically decrements the address; if reset(0) the string address will be incremented :::success **Maskable interrupt(可遮罩) v.s. Non-Makable interrput(不可遮罩)** Maskable interrupt : 可以藉助軟體指令(例如 8088 之 CLI，STI 指令)，控制 CPU 是否要處理中斷指令。**以遮罩的方式來關閉中斷封鎖暫存器。** Non-Maskable interrupt : 不可藉助軟體指令抑制，強迫 CPU 一定要處理的中斷。**無法通過在中斷封鎖暫存器時，設定位遮罩來關閉。** > 例如去ATM提款：領錢(必須領完)$\rightarrow NMI$，看到同學打招呼(可以忽略)$\rightarrow MI$ ::: Generating a memory address --- + Logical address + Segment base and an offset (16bits and 16 bits) + Physical address + Is used to access memory (20bits, address bus) Translating logical address into physical address + Source of offset value depends on which type of memory reference is taking place + BP and SP for stack segment + BX, SI and DI for data and extra segment + IP for code segment ![memory-address](https://i.imgur.com/bGQ7OuS.jpg =200x) + CS：code segment + CS：IP point to next address of instruction + DS and ES：data segment + point to address of desired data + DS：SI or DS：DI + ES：SI or ES：DI + DS：BX or ES：BX (少見) + DS：BP or ES：BP (少見) + SS：stack segment + SS：SP ![address](https://i.imgur.com/isobcex.png =400x) Segment base value and an offset value are combined to form a physical address $$Segment * 16 + Offset$$ :::warning **Example** CS = 0100H, IP = 0204H The physical address of `next instruction` are 01204h ::: ![physical](https://i.imgur.com/r3ol9TX.jpg =400x) The stack --- + First In Last Out (FILO) + 暫時存放Data的地方 + Usually used in call subroutine (呼叫副程式) + All contents of other registers may also be saved + All parameters for subroutine + Callee can access parameters using SS：BP + Push & Pop instruction ![ss](https://i.imgur.com/ajZHQ3l.jpg =400x) 主程式呼叫副程式 ![stack](https://i.imgur.com/VcWHZ1i.jpg) + 呼叫副程式時，把main的$CS_1:IP_1$Push進Stack裡，並換成副程式的$CS_2:IP_2$ + Return後，Pop出Stack，得到上一個的$CS_1:IP_1$，然後$CS_2:IP_2$指向$CS_1:IP_1$ + 如果函式有傳值，則利用BP去複製值 SP contains an offset value `initialized to FFFEH` + SS：FFFEH `bottom of stack` + SS：0000H `end of stack` + SS：SP `top of stack` > Data transferred to and from the stack are `word-wide`, not byte-wide ![ss-sp](https://i.imgur.com/fh3rAeX.jpg =300x) + Push onto the top of the stack + the value in SP is first automatically decremented by two (自動減二) + Contents of the register are written into the stack part of memory + PUSH AX + SS：SP = 0105:0008 - 2 = 0156 ![push](https://i.imgur.com/qZmbcjS.jpg =400x) + POP from the top of stack + SP is automatically incremented by two (自動加二) + Contents are first popped off the stack and put into the specific register within the 8088 + POP AX + [SS:SP] = 1234h -> AX + SP + 2 -> SP (放回) ![pop](https://i.imgur.com/04VXniZ.jpg =400x) Input/Outpot address space --- 8086/8088 has `separate memory and IO address spaces` > 參考8086/8088之接腳 IO mapped IO + Separated IO address + Separated IO instruction + In/OUT (IO指令) + IO接腳 Memory mapped IO + Shared memory + Same as memory instruction Can be byte-wide or word-wide access 有些CPU把記憶體與IO看成同一種元件 有些CPU把記憶體與IO看成不同種元件 > IO mapped IO v.s. Memory mapped IO ![io-memory](https://i.imgur.com/BTDqLlc.jpg) 參考資料 + Barry B. Bery, “The Intel Microprocessors,” 8th Edition, 2009, Prentice Hall. + Walter A. Triebel, Avtar Singh, “The 8088 and 8086 Microprocessors – Programming, Interfacing, Software, Hardware, and Applications,” 4th Edition, 2003, Prentice Hall. + 國立臺北大學資工系張玉山教授ppt