---
# System prepended metadata

title: IOP Address Generator

---

# IOP TapRAM Address Generator

## FFT
We have 9 stage FFT(5 BPE for 100% SDF).
```
512 twiddle factor stored in memory.
//-----stage-----//
stage 1: memory address access minimum interval = 512/2^1 = 256

ex: **W0** W256(round every 2^1 twiddle factor)
//---------------//

//-----stage-----//
stage 2: memory address access minimum interval = 512/2^2 = 128

ex: **W0 W128** W256 W384(round every 2^2 twiddle factor)
//---------------//

//-----stage-----//
stage 3: memory address access minimum interval = 512/2^3 = 64

ex: **W0 W64 W128 W192** W256 W320 W384 W448(round every 2^3 twiddle factor)
//---------------//

//-----stage-----//
stage 4: memory address access minimum interval = 512/2^4 = 32

ex: W0 W32 W64 W96 W128...(round every 2^4 twiddle factor)
//---------------//

//-----stage-----//
stage 5: memory address access minimum interval = 512/2^5 = 16

ex: W0 W16 W32 W48 W64...(round every 2^5 twiddle factor)
//---------------//

//-----stage-----//
stage 6: memory address access minimum interval = 512/2^6 = 8

ex: W0 W8 W16 W24 W32...(round every 2^6 twiddle factor)
//---------------//

//-----stage-----//
stage 7: memory address access minimum interval = 512/2^7 = 4

ex: W0 W4 W8 W12 W16...(round every 2^7 twiddle factor)
//---------------//

//-----stage-----//
stage 8: memory address access minimum interval = 512/2^8 = 2

ex: W0 W2 W4 W6 W8...(round every 2^8 twiddle factor)
//---------------//

//-----stage-----//
stage 9: memory address access minimum interval = 512/2^9 = 1

W0 W1 W2 W3 W4...(round every 2^9 twiddle factor)
//---------------//
```
Note: minimum interval means the address difference between two access.

Every twiddle factor correspond to a pair of input to BPE.

Only need twiddle factor before 256.

## iFFT
```
512 twiddle factor stored in memory.
//-----stage-----//
stage 1: memory address access minimum interval = 512/2^9 = 1

W0 W1 W2 W3 W4...(round every 2^9 twiddle factor)
//---------------//

//-----stage-----//
stage 2: memory address access minimum interval = 512/2^8 = 2

ex: W0 W2 W4 W6 W8...(round every 2^8 twiddle factor)
//---------------//

//-----stage-----//
stage 3: memory address access minimum interval = 512/2^7 = 4

ex: W0 W4 W8 W12 W16...(round every 2^7 twiddle factor)
//---------------//

//-----stage-----//
stage 4: memory address access minimum interval = 512/2^6 = 8

ex: W0 W8 W16 W24 W32...(round every 2^6 twiddle factor)
//---------------//

//-----stage-----//
stage 5: memory address access minimum interval = 512/2^5 = 16

ex: W0 W16 W32 W48 W64...(round every 2^5 twiddle factor)
//---------------//

//-----stage-----//
stage 6: memory address access minimum interval = 512/2^4 = 32

ex: W0 W32 W64 W96 W128...(round every 2^4 twiddle factor)
//---------------//

//-----stage-----//
stage 7: memory address access minimum interval = 512/2^3 = 64

ex: W0 W64 W128 W192 W256 W320 W384 W448(round every 2^3 twiddle factor)
//---------------//

//-----stage-----//
stage 8: memory address access minimum interval = 512/2^2 = 128

ex: W0 W128 W256 W384(round every 2^2 twiddle factor)
//---------------//

//-----stage-----//
stage 9: memory address access minimum interval = 512/2^1 = 256

ex: W0 W256(round every 2^1 twiddle factor)
//---------------//
```

## NTT

## iNTT