---
# System prepended metadata

title: Verilog 學習筆記
tags: [Verilog, book]

---

<!-- 
:::::spoiler 快速目錄
> [!Note] 目錄
> :::spoiler **[● 設計觀念](#●-設計觀念)**
> - [IC 設計流程](/@C2N2/SJKDZss8ge)
> - [Synopsys Design Constraints (.sdc)](/@C2N2/rkrVNgYLxe)
> - [Retiming](/@C2N2/BJfZCkjIel)
> - [Design for Testability (DFT)](.)
> :::
> ---
> ::::spoiler **[● Verilog 設計](#●-Verilog-設計)**
> :::spoiler **[Verilog 教學](#Verilog-教學)**
> - [01. Verilog 基本架構](/@C2N2/SJwE1QnSxe)
> - [02. Verilog 設計層次](/@C2N2/HyBH1QnBge)
> - [03. Veriolg 運算子](/@C2N2/rkprk73Hgl)
> - [04. 變數處理](/@C2N2/SJN1gEhHll)
> - [05. 程式區塊](/@C2N2/SkMwzE3Sxl)
> - [06. 階層化設計](/@C2N2/HJ0CX4nrgg)
> - [~~07. Generate~~](/@C2N2/rJv3YEnHxg)
> - [08. Testbench](/@C2N2/SyELyX2rxe)
> :::
> ---
> :::spoiler **[Verilog 設計方法](#Verilog-設計方法)**
> - [01. 程式風格](/@C2N2/r1uP_-aSll)
> - [02. FSM (Finite State Machine)](/@C2N2/BJ4se7aSxe)
> - [03. Resource Reuse](/@C2N2/r1xvuvyUgx)
> - [04. Pipeline](/@C2N2/HkPF_PkUge)
> :::
> ::::
> ---
> ::::spoiler **[● 設計工具](#●-設計工具)**
> :::spoiler **[設計環境](#設計環境)**
> - [01. cmd 基本指令](/@C2N2/Sy_pRfhSxe)
> - [02. 檔案權限](/@C2N2/Hyog1X2Bee)
> - [03. Vi 編輯器](/@C2N2/SyTQyQ2Bex)
> :::
> ---
> :::spoiler **[EDA tool](#EDA-tool)**
> - [ncverilog](/@C2N2/r1UDyZmLlg)
> - [nWave](/@C2N2/r1gExQ78xg)
> - [Spyglass](/@C2N2/SkxLg_X8ge)
> - [Design Compiler](/@C2N2/rJOgEeNUgl)
> - [Design Vision (Intro)](/@C2N2/B1KM654Lgg)
> - [dv.1 (Create Design)](/@C2N2/ByWb6adLee)
> - [dv.2 (Design Condition)](/@C2N2/rkjnZj8Ulg)
> - [dv.3 (Design Environment)](/@C2N2/rk8C-s88xe)
> - [dv.4 (Compiler & Save)](/@C2N2/HJO6fiILlg)
> - [DFT & TetraMax](/@C2N2/BJcS2yi8ll)
> - [Code Coverage](.)
> - [Innovus](.)
> :::
> ---
> :::spoiler **[VS Code 工具設定](#VS-Code-工具設定)**
> - [VS Code Download](http://code.visualstudio.com/Download)
> - [Verilog 語法偵錯工具](/@C2N2/S11zfAlIex)
> - [格式化工具 1：iStyle](/@C2N2/rJeNsy-Ulg)
> - [格式化 2:]
> - [格式化 3:]
> - [SSH 連線工具](/@C2N2/HktOZeb8ll)
> :::
> ::::
> ---
> ::::spoiler **[● 其他內容](#●-其他內容)**
> :::spoiler **[訓練內容](#●-訓練內容)**
> - [暑期訓練 07/04](/@C2N2/rkcja03Hel)
> - [暑期訓練 07/07](/@C2N2/Hk5TBgTHge)
> - [暑期訓練 07/09](/@C2N2/rJ7b9eaHgl)
> - [Example](/@C2N2/B1_KzX3Bex)
> :::
> ---
> :::spoiler **[參考資料](#●參考資料)**
> - [📘Digital IC Design](http://hackmd.io/@derek8955/BkK2Nb5Jo)
> :::
> ::::
:::::
-->

# Verilog 學習筆記

## 目錄
- [首頁 - Verilog 學習筆記](/@C2N2/ByfB0znrgg)
- [📘程式學習筆記](http://hackmd.io/@C2N2/rJ3XFtZC1g)

---

# 設計觀念

> [Top](#Verilog-學習筆記)

- [IC 設計流程](/@C2N2/SJKDZss8ge)
- [Synopsys Design Constraints (.sdc)](/@C2N2/rkrVNgYLxe)
- [Retiming](/@C2N2/BJfZCkjIel)

---

# Verilog 設計

> [Top](#Verilog-學習筆記)

- [📘Verilog 語法](https://hackmd.io/@C2N2/BJXL7V6iee)
- [📘Verilog 設計觀念](https://hackmd.io/@C2N2/SJSsXNTigx)

---

# 設計工具

> [Top](#Verilog-學習筆記)

- [📘Verilog 設計環境](https://hackmd.io/@C2N2/HyxMHETiel)
- [📘EDA tool](https://hackmd.io/@C2N2/BybGH4aogg)
- [📘VS Code 工具設定](https://hackmd.io/@C2N2/rkWMB4pjex)

---

# 其他內容

> [Top](#Verilog-學習筆記)

## 練習

- [暑期訓練 07/04](/@C2N2/rkcja03Hel)
- [暑期訓練 07/07](/@C2N2/Hk5TBgTHge)
- [暑期訓練 07/09](/@C2N2/rJ7b9eaHgl)
- [Example](/@C2N2/B1_KzX3Bex)

## 參考資料

- [📘Digital IC Design](http://hackmd.io/@derek8955/BkK2Nb5Jo)

---