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# System prepended metadata

title: ASIC Project

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# ASIC Project

## EECS 151/251A ASIC Project Specification: Checkpoint 1
1. Making a pipeline diagram
- Found in asic-pipeline_diagram.pdf

2. ALU functional specification
3. Project Files
4. Testing the Design
    4.1 Verilog Testbench
    4.2 Test Vector Testbench
    4.3 Writing Test Vectors
5. Writing Verilog Modules
6. Running the Simulation
7. Viewing Waveforms
8. Checkpoint #1: Simple test program
- What bugs, if any, did your test bench help you catch?
    **Sol**: We found a bug where we always want to perform the `ALU_ADD operation  when we are dealing with I_type instructions that our original implementation did not have.
- For one of your bugs, come up with a short assembly program that would have failed had you not caught the bug. In the event that you had no bugs and wrote perfect code the first time, come up with an assembly program to stress the SRA bug mentioned in the above section.
    **Sol**: addi x1 x0 1000; addi x2 x1 -2000; as this subtracted the negative numbers which gave us the wrong value!