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# System prepended metadata

title: lab4-0 知識

---

# lab4-0 知識
caravel soc:
![](https://hackmd.io/_uploads/SyXO3FbGp.png =80%x)

mprj是啥?
## Caravel SOC - SRAM
sram
- storage (memory) connected by the wishbone interface

memory description

![](https://hackmd.io/_uploads/BkeFZqbM6.png)
- sram usage
   - dff, executable data section
      - .data 先存flash 在搬到dff
      ![](https://hackmd.io/_uploads/rkWmMq-GT.png)

      - .bss 
      ![](https://hackmd.io/_uploads/HkWEzcZMp.png)

   - dff2, slack

executable data initialization
firmwave 先存在SPI，在拷貝到dff。

## Caravel SOC - Wishbone
- System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores
- Purpose - Fostering design reuse by alleviating SoC integration problems
- Caravel SoC applied Shared bus interconnection methods
- WISHBONE Signals
  - SYSCON
    - RST_O
    - CLK_O
  - Common for both MASTER/SLAVE
    - RST_I
    - CLK_I
    - DAT_I(), DAT_O()
  - MASTER
    - ADR_O(), WE_O, SEL_O() (selection), STB_O (strobe觸發), ACK_I, CYC_O() 總線周期的開始
  - SLAVE
    - ADR_I(), WE_I, SEL_I(), STB_I, ACK_O, CYC_I
    
    ![](https://hackmd.io/_uploads/r1bPjqMMa.png)
     master:red slave blue

- Signals to WISHBONE Bus @VexRiscv

  ![](https://hackmd.io/_uploads/H1KQeKfG6.png)

ibus(master):會右移2

dbus(msater):會右移2

reference:https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/

- Round-robin for WB requests @Management Core
  - wire [2:0] request; // 3個master 3 bit 
    assign request = {dbg_uart_wishbone_cyc, mgmtsoc_dbus_dbus_cyc, mgmtsoc_ibus_ibus_cyc};
  - reg [1:0] grant = 2'd0; //"grant"訊號在 Wishbone 匯流排中用於管理和指派匯流排存取權限，以確保多個裝置可以按照一定的順序共用匯流排存取機會。
  
  ![](https://hackmd.io/_uploads/ry30utGGp.png)

  ![](https://hackmd.io/_uploads/rkrktFMf6.png)

  ![](https://hackmd.io/_uploads/HkR1YFfGa.png)

- WISHBONE Share Signals @Management Core
  - WISHBONE Shared Signals (shared_xxx)
    - Output:
      shared_adr, shared_dat_w, shared_sel, shared_cyc, shared_stb, shared_we, shared_cti, shared_bte
    -  Input:
       shared_ack, shared_dat_r
       ![](https://hackmd.io/_uploads/HJCV6qMG6.png)
- WISHBONE Signals for Slaves @Management Core
  - WISHBONE slave selection
    - reg [6:0] slave_sel
      Partial Decoding
    - Slave’s CYC
      shared_cyc & slave_sel[n]
      ![](https://hackmd.io/_uploads/Bk941jMfT.png)
      ![](https://hackmd.io/_uploads/HJZeeoMG6.png)
  - Signals of each WISHBONE Slaves
    ![](https://hackmd.io/_uploads/By8tgiMMa.png)
    ![](https://hackmd.io/_uploads/SkX5xsfzT.png)
    ![](https://hackmd.io/_uploads/r1coxjfz6.png)
    
- WISHBONE Signals for User Project Slave @Management Core
  - Signals to User Project WISHBONE
    - OUTPUT:
      mprj_cyc_o , mprj_stb_o, mprj_we_o, mprj_sel_o, mprj_adr_o, mprj_dat_o
      - 30bits address to 32bits here
      -  From mprj_cyc, mprj_stb, mprj_we, mprj_sel, mprj_adr, mprj_dat_w (from shared_xxx)
    - Input:
      mprj_ack_i, mprj_dat_i
       - To mprj_ack, mprj_dat_r (to shared_xxx)
       
      ![](https://hackmd.io/_uploads/HJ3yNiMzp.png)
- WISHBONE Signals for User Project Slave @Management Core Wrapper
  - Signals to User Project WISHBONE
    - OUTPUT:
      mprj_cyc_o , mprj_stb_o, mprj_we_o, mprj_sel_o, mprj_adr_o, mprj_dat_o
       - From mprj_cyc_o , mprj_stb_o, mprj_we_o, mprj_sel_o, mprj_adr_o, mprj_dat_o (from Management Core)
    - Input:
      mprj_ack_i, mprj_dat_i
       - To mprj_ack, mprj_dat_i (to Management Core)
       
      ![](https://hackmd.io/_uploads/S1k2VoGfp.png)
- WISHBONE Signals for User Project Slave @Carval 
  - Signals to User Project WISHBONE
    - OUTPUT:
     mprj_cyc_o_core (user), mprj_stb_o_core (user), mprj_we_o_core (user),
       - From mprj_cyc_o , mprj_stb_o, mprj_we_o, mprj_sel_o, mprj_adr_o, mprj_dat_o (from Management Core Wrapper)
    - Input:
      mprj_ack_i_core (user), mprj_dat_i_core (user)
       - To mprj_ack_i, mprj_dat_i (to Management Core Wrapper)

總結，以user_project slave為例，CPU發起前往slave cyc時，會先經過request的仲裁，在取得bus的使用權，相對應的wishbone's signal 會送到wishbone bus上，此時會經過management core slave selection decode ，對於user_project stb訊號 assert，最後user_project cyc跟stb為1時響應。

![](https://hackmd.io/_uploads/ryAkQhzGT.png)

## Caravel SOC - User Project Design Interface
- Introduction
  - User Project Wrapper
    - Providing the interface between Management Core and User Project
      - Wishbone: Range 0x30000000 ~ 0x3FFFFFFF
      - Logic Analyzer [127:0]
      - MPRJ_IO [37:0]
      - User Clock
      - IRQ [2:0]
    - User Project Wrapper Implementation([user_project_wrapper.v](https://github.com/bol-edu/caravel-soc/blob/main/rtl/user/user_project_wrapper.v))
      ![](https://hackmd.io/_uploads/rybEPhGMp.png)
- lab實做(Counter - LA and Counter - WB)
  - Counter - LA
    - [counter_la_tb.v](https://github.com/bol-edu/caravel-soc/blob/main/testbench/counter_la/counter_la_tb.v)
    - [counter_la.c](https://github.com/bol-edu/caravel-soc/blob/main/testbench/counter_la/counter_la.c)
    - [user_proj_example.counter.v](https://github.com/bol-edu/carave-soc/blob/main/rtl/user/user_proj_example.counter.v)
  - Counter - WB

## Caravel SOC - Peripherals-Counter timer/UART
- Counter timer
   - 三種模式
      polling: returns current countdown value to software
      one-shot: loads itself and stop when value reach 0
      periodic: reloads itself when value reaches 0
  - register
  
    ![](https://hackmd.io/_uploads/SkYDOiozp.png)

    load 跟 reload (差在用one shot or periods), it will be loaded to value register when en is 1, and reload when timers reach 0 (periods時)
    update value: a wire to this register latches the currentdown value to value register
    value: latched countdown value.
    ev_status:為0舉為1
  - example 
    oneshot mode:
    
    ![](https://hackmd.io/_uploads/B1GYZ3iza.png)

    periods mode:
    
    ![](https://hackmd.io/_uploads/HJ2cZ2jGa.png)

- UART
  - The UART provide general serial communication with the management SoC. The baud rate is configured at 9600 bps (104.2us per bit).
    ![](https://hackmd.io/_uploads/SJnAaTsfa.png)
  - Protocol Format
  
    ![](https://hackmd.io/_uploads/HkPl0ajG6.png)
  - For Carvel:
    Data bits:8
    Parity bit:0
    Stop bit:1
  - tx(pin F7) and ser rx (pin E7)
    Although the UART operates independently of the CPU, data transfers are blocking operations which will generate CPU wait states until the data transfer is completed.
    - Transmit data: reg_uart_data = “c”; Writing a value to this register will immediately start a data transfer on the ‘<ser_tx>` pin. If the UART write operation is pending, then the CPU will be blocked with wait states until the transfer is complete before starting the new write operation.
    - Receive data: Returns 255 (0xff) if no valid data byte ; or returns the value of the received buffer otherwise, and clears the receive buffer for additional reads..
    - Note that there is no FIFO associated with the UART
  - register
    ![](https://hackmd.io/_uploads/By-VyRjfp.png)

  - example
    ![](https://hackmd.io/_uploads/HJ6sy0iMa.png)

    
    
     
