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# System prepended metadata

title: 'asoc 所有相關筆記:'

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# asoc 所有相關筆記:
期末內容:
https://hackmd.io/De-TPbOLQJG8Gj2lIJnQaQ
https://hackmd.io/lH0-NF4_To6SVMHeZvN74g
https://hackmd.io/ZuPyFhLKQqO-ojhOdne7Dg 
上課ppt整理
# Crosstalk/Noise Analysis

## Key Concepts and Terminologies
- **Crosstalk**: The impact of noise or interference within circuits, often involving adverse interactions between adjacent signal lines.
- **Stage Delay**: The delay of a stage includes both the cell and net delay.
- **Timing Windows**: Defines the timing window for each stage, based on the shortest and longest path delays leading up to that net (OCV is used).

## Crosstalk Analysis Essentials
- **Overlapping Timing Windows**: Occurs when victim nets switch around the same time as aggressor nets.
- **Delta Delay**: Delay caused by switching aggressor/victim nets with overlapping timing windows. Can be positive (slowdown) or negative (speed up).
- **Switching Bump**: A measure expressed as a ratio of VDD, used to calculate delta delay on a victim.

## Setup for Crosstalk Analysis
- **Operating Conditions**: Use the command `set_operating_conditions -analysis_type on_chip_variation` for setting the conditions under which the analysis is conducted.
- **Reading Parasitics**: It's crucial to use SPEF or GPD files with coupling capacitances (`read_parasitics -keep_capacitive_coupling SPEF.spf`).

## Crosstalk Delay Calculation Using CCS Models
- Utilize CCS models for gate-level simulation to account for the distorted waveform due to crosstalk.
- **Output Delay Calculation**: Based on the CCS model; if no CCS model for the receiver, the input delay is calculated.

## Clock Relationships and Constraints
- **Asynchronous Clocks**: Analyzed conservatively causing delta delay due to crosstalk.
- **Logically Exclusive Clocks**: Analyzed for possibly causing delta delay due to crosstalk.
- **Physically Exclusive Clocks**: Do not co-exist in the design simultaneously to be affected by functional paths or crosstalk between them.

## Advanced Commands for Analysis
- `set_clock_group –asynchronous  –group [CLKA CLKA_div2]  –group CLK_OSC`: For defining asynchronous clock groups.
- `create_clock -name CLK_FUNC [get_ports CLK] -period 6`: For creating clocks with specific periods and characteristics.

## Noise Analysis
- **Unsafe Noise Bumps**: If the noise bump crosses the logic threshold, it may cause a functional failure.
- **Noise Margin and Immunity**: Describes the amount of noise that can be tolerated without causing a logic failure.

## Use of Statistical Composite Aggressor Mode
- This mode lumps filtered aggressors together into a single "composite aggressor" for a statistically modeled inclusion in victim SI analysis.

## Practical Tips
- Ensure the quality of parasitic data annotation and completeness of constraints to improve the accuracy of crosstalk analysis.
- Utilize electrical filtering to screen out aggressor nets with minimal impact on the final results.

# On-Chip Variation (OCV) Analysis

## Overview
- **OCV**: Introduced for technology nodes below 90nm to address spatial and PVT (Process/Voltage/Temperature) variations.
- **AOCV**: Advances in OCV to account for variations by depth and distance within the chip.
- **POCV**: Models random variations using a Gaussian Distribution for each cell, moving beyond AOCV's limitations.

## Key Concepts
- **Spatial Variation**: Differences in chip areas can cause varying delays in timing paths.
- **Traditional Approach**: Uses a conservative setup and hold analysis, applying global derates across the design.

## Detailed Analysis Types
### OCV
- Uses global derates; too pessimistic as it does not consider individual path or cell variations.
- Example command: `set_timing_derate –early 0.9 –late 1.2`

### AOCV
- Accounts for cell depth and location, applying specific derates based on path depth and distance.
- Command: `set_timing_aocvm_enable_analysis true`

### POCV
- Utilizes individual cell delay distributions to statistically model delay variations, eliminating path depth pessimism.
- Important for designs at 16nm and below due to its high accuracy and reduced pessimism.
- Example usage: `report_ocvm –type pocvm [get_cell XX]`

## Advanced Waveform Propagation (AWP)
- Addresses waveform distortions in advanced nodes due to effects like the Long Tail and Strong Backward Miller Effect.
- Enhances timing accuracy by reproducing actual waveform shapes observed in circuit simulation.
- Example setup: `set delay_calc_enhanced_ccsn_waveform_analysis true`

## Practical Applications
- **CRPR (Clock Reconvergence Pessimism Removal)**: Applied to reduce the pessimism by removing derating from shared clock paths.
- **Guardbanding and Scaling in POCV**: Adjusts both mean delays and variation to account for non-process related effects.

## Commands and Techniques
- **Setting OCV Analysis**: `set_db timing_analysis_type ocv`
- **Enabling AOCV Analysis**: `timing_aocvm_enable_analysis`
- **Applying POCV**: Uses LVF (Liberty Variation Format) to provide cell-specific variation models.

## Conclusion
- The evolution from OCV to AOCV, and then to POCV, shows significant improvements in modeling on-chip variations, reducing pessimism and enhancing design accuracy especially in advanced technology nodes.
# Low Power Verification Using UPF

## Overview
- **Topics Covered**:
  - Power Distribution & Strategy in UPF definition
  - Multivoltage design components
  - Synopsys Low Power Verification Flow
  - An UPF Design Example

## Key Concepts

### Functional vs. Power Intent
- **Functional Intent**: Architecture, design hierarchy, data paths, usage of IP, and custom blocks.
- **Power Intent**: Power distribution architecture, power domains, supply rails, shutdown control, and use of special cells like isolation cells, level shifters, and retention registers.

### UPF Terminology
- **Power Domain**: A logical partition with common power characteristics defined using `create_power_domain`.
- **Power Supply Network**: Consists of supply nets, supply ports, and supply switches. Commands include `create_supply_net` and `create_supply_port`.
- **Special Cells**: Include level shifters, isolation cells, power switches, and retention registers, each essential for addressing specific power-related design challenges.

## Power Strategy Components

### Power Domains and Supply Networks
- Domains and networks are defined using UPF commands to ensure proper power distribution and isolation within the design.

### Level Shifters
- Critical for interfacing between domains of different voltage levels. Commands used include `set_level_shifter` and `map_level_shifter_cell`.

### Isolation Cells
- Protect circuits by ensuring that inactive states do not affect active states, especially in power-down scenarios. Implemented using commands like `set_isolation` and `map_isolation_cell`.

### Power Switches
- Used to reduce leakage power by disconnecting the power supply during inactive states. Defined with `create_power_switch`.

### Retention Registers
- Preserve the state of design elements during power down to enable quick recovery. Setup involves `set_retention` and `map_retention_cell`.

## Design Examples and Considerations

### Example Design Flow
- Define power domains and supply networks.
- Implement power management techniques using level shifters, isolation cells, and power switches.
- Set up retention strategies to maintain state information during low power states.

### Verification and Debugging
- Synopsys provides tools like VC Static LP for rule checking and VCS NLP for simulation, ensuring that the power intent is correctly implemented and functional across various power states.

## Practical Applications
- **Golden UPF Flow**: Ensures that the UPF file remains consistent throughout the design process, facilitating easier updates and maintenance.
- **UPF Verification Flow**: Involves checks at both RTL and netlist levels to prevent signal corruption and ensure structural integrity.

## Conclusion
- Using UPF for low power verification allows for comprehensive management of power in complex designs, ensuring energy efficiency and reliability in modern electronic systems.
# UVM Introduction

## Overview
UVM (Universal Verification Methodology) is a standardized methodology for verifying integrated circuit designs. It is built on top of SystemVerilog and provides a framework for developing testbenches that are reusable, scalable, and interoperable.

## Key Concepts and Components

### SystemVerilog Interface
- **Purpose**: Facilitates communication between modules and testbenches.
- **Usage**:
  - Define the interface.
  - Create a class containing a virtual interface.
  - Instantiate the interface and access signals through it.

### UVM Components and Tests
- **UVM Test**: Central component for initiating and controlling simulations.
- **Steps**:
  - Extend `uvm_test`.
  - Create and utilize a package variable for the interface.
  - Configure and stimulate the DUT (Device Under Test) in `build_phase()` and `run_phase()` tasks.

### UVM Environment
- **Purpose**: Houses the components and sequences that drive the verification process.
- **Configuration**:
  - Use `.svh` files for class declarations.
  - Organize and include these files in a UVM package.

### Producer-Consumer Model
- **Model**: Utilizes OOP concepts like ports, exports, and TLM FIFOs to manage data transactions between producer and consumer components in a UVM testbench.

### UVM Transactions
- Represents data being transferred within the testbench, typically extending from `uvm_transaction`.

### UVM Reporting
- **Functionality**: Provides mechanisms for outputting simulation data and diagnostics.
- **Features**:
  - Formatting and system calls.
  - File operations.
  - Detailed control over reporting verbosity and filters.

### Functional Coverage
- **Purpose**: Enhances code coverage with user-defined metrics to ensure all functional scenarios are tested.
- **Implementation**:
  - Use the `covergroup` keyword.
  - Define bins and cross bins to track scenarios of interest.

### Sequences
- **Purpose**: Manages the generation of stimulus data sent to the DUT.
- **Components**:
  - `uvm_sequencer` for controlling sequence execution.
  - Sequences and drivers to generate and send transactions.

## Learning Resources
- Mentor UVM Course, UVM Primer, YouTube tutorials, and GitHub repositories provide extensive material for self-learning UVM.

## Practical Application
- **Simulation Flow**:
  - Define interfaces and package structures.
  - Implement test components and environment settings.
  - Execute tests to validate DUT behavior under various conditions.

## Conclusion
UVM provides a robust framework for verifying complex system designs, facilitating thorough testing and ensuring high-quality hardware development.


# I/O Design in SOC

## Overview
This document covers the essential aspects of I/O design for System on Chips (SOC), focusing on buffer cells, signaling, protection mechanisms, and layout considerations.

## Key Topics
- **I/O Buffer Cells**: Different types include output, input, and bidirectional.
- **I/O Ring**: Essential for reliability, protecting against various failures such as ESD and latch-up.
- **Protection Mechanisms**: ESD protection, clamp of supply line, and mechanisms to handle overstress voltages and currents.
- **Signaling Techniques**: Covers differential signaling, slew rate effects, and transmission line considerations.

## I/O Buffer Cells
- Designed to handle large off-chip loads with suitable rise and fall times.
- Incorporates features to prevent latch-up and manage noise levels.
- Includes structures like inner guard rings (p+) and outer guard rings (n+) in n-well for enhanced protection.

## I/O Ring and Layout
- **Function**: Protects the integrity of the SOC by providing structured pathways for power and signals.
- **Components**: Includes VDD/GND, input, output, bidirectional, and analog paths.
- **Layout Considerations**: Focuses on pad configurations such as in-line and staggered, and specialized structures for flip-chip designs.

## Protection from Latch-up and ESD
- **Latch-up Protection**: Techniques to reduce the amplification of parasitic bipolar transistors, crucial for CMOS technology.
- **ESD Protection**: Strategies to safeguard against electrostatic discharges, including using diodes and specific transistor structures to manage high current densities and prevent thermal damage.

## Signaling and Transmission
- **Differential Signaling**: Utilized for its robustness against noise and its ability to maintain consistent current flow, enhancing signal integrity.
- **Transmission Lines**: Considerations include the characteristic impedance, signal reflection, and the use of terminations to prevent signal degradation.

## Slew Rate and Signal Integrity
- Discusses the trade-offs between signal speed and quality, emphasizing the importance of controlling slew rates to minimize issues such as crosstalk and EMI.
- Provides guidelines for achieving optimal signal integrity through careful PCB layout and component selection.

## Conclusion
The document serves as a comprehensive guide to the critical elements of SOC I/O design, offering insights into effective design strategies to enhance reliability, performance, and compatibility in modern electronics.

# SerDes in SOC Design

## Overview
This document discusses Serializer/Deserializer (SerDes) technology in System on Chip (SOC) design, covering the architecture, technologies, and challenges in high-speed data transmission.

## Key Topics
- **SerDes Architecture**: Includes Serializer, Deserializer, Clock Manager, and associated technologies.
- **Types of I/O Timing**: System-Synchronous, Source-Synchronous, and Self-Synchronous.
- **Line Encoding Techniques**: For DC-balance and clock recovery.
- **Physical Signaling**: Utilizes differential transmission lines with pre-emphasis and de-emphasis techniques.
- **Inter-symbol Interference (ISI)**: Challenges and solutions for data integrity.

## SerDes Architecture
- **Serializer**: Converts parallel data to serial form.
- **Deserializer**: Converts serial data back to parallel form.
- **Clock Manager**: Manages clock signals across Serializer and Deserializer for accurate data recovery.

## I/O Timing Models
- **System-Synchronous**: Both transmitting and receiving ICs use a common clock.
- **Source-Synchronous**: Includes a clock forwarded along with the data for synchronization.
- **Self-Synchronous**: Data and clock are encoded together, reducing reliance on separate clock lines.

## Line Encoding for DC-balance
- **Purpose**: Ensures that the transmitted signal has minimal DC component, reducing power consumption and electromagnetic interference.
- **Techniques**: Utilizes various encoding schemes to balance the ones and zeros in a data stream, such as 8b/10b encoding.

## Differential Signaling
- **Advantages**: Reduces susceptibility to noise and electromagnetic interference.
- **Implementation**: Utilizes pairs of signals with opposite polarities to improve signal integrity.

## Challenges in High-Speed Data Transmission
- **Inter-symbol Interference**: Caused by signal reflections and crosstalk, managed by careful PCB design and signal conditioning techniques.
- **Channel Bonding and Lane Deskew**: Techniques to align data lanes, improving data throughput and reliability.

## Physical Layer Enhancements
- **Pre-emphasis/De-emphasis**: Techniques to compensate for signal loss over transmission media.
- **Line Equalization**: Adjusts the signal properties to counteract the dispersion and loss in the transmission path.

## Practical Applications
- **SerDes in High-Speed Networking**: Essential for applications requiring fast data transfer rates, such as in data centers and high-performance computing.
- **Automotive and Industrial Applications**: Critical for safety and reliability in environments with high electromagnetic interference.

## Conclusion
The document provides a comprehensive overview of SerDes technology, highlighting its importance in modern SOC design and its role in enhancing data communication integrity and efficiency.

# SOC Power Management

## Overview
This document discusses various aspects of power management in System on Chip (SOC) designs, focusing on power distribution, noise reduction, and packaging effects.

## Key Concepts and Topics
- **Power Distribution**: Techniques for managing power delivery across different components of the SOC.
- **IO and Core Power**: Differences in power requirements and management between I/O interfaces and the core processing units.
- **Electromigration**: Considerations for preventing damage due to the movement of metal ions under high current densities.
- **Power Noise Reduction**: Strategies to mitigate noise generated by power fluctuations and switching.

## Power Distribution Techniques
- **Power Grid Design**: Specifications for metal width and spacing in the power grid to ensure efficient and stable power delivery.
- **Decoupling Capacitors**: Their use in stabilizing power supply by mitigating voltage spikes and drops.
- **IR-Drop and Electromigration**: Addressing voltage drop across power lines and movement of metal due to high current densities.

## Packaging and Its Effects
- **Types of IC Packages**: Impact of different packaging technologies like Wire-bond, Flip-chip, and Multi-Chip Modules on power integrity and performance.
- **Package Inductance and Resistance**: How these factors affect signal integrity and power distribution.

## Noise Reduction Techniques
- **Simultaneous Switching Outputs (SSO)**: Management of noise due to multiple I/O ports switching simultaneously.
- **Placement of Power and Ground Pins**: Optimizing layout to minimize noise and ensure robust power delivery.

## Challenges and Solutions
- **Electromigration**: Strategies to prevent damage from high current densities, such as using wider metal lines and choosing materials with higher current carrying capacity.
- **Power-up/Power-down Sequences**: Proper sequencing to avoid power spikes and ensure component safety.

## Practical Implementations
- **Hot-plug Protection**: Ensuring SOC components can be safely added or removed without shutting down the system or causing electrical damage.
- **Voltage Regulation**: Techniques to maintain consistent voltage levels across various parts of the SOC despite fluctuations in load and input power.

## Conclusion
Effective power management is crucial for the reliability and performance of SOCs, requiring careful consideration of layout, component placement, and materials to ensure stable operation and longevity of the device.

# Reset in SOC Design

## Overview
This document discusses the various reset mechanisms used in System on Chip (SOC) designs, focusing on their applications, benefits, and challenges across different domains and processes.

## Key Topics
- **Types of Resets**: Differentiates between synchronous and asynchronous resets.
- **Reset Domain Crossings (RDC)**: Issues and solutions for resets across multiple clock domains.
- **Power-on Reset (POR)**: Implementation and significance in ensuring reliable system startups.

## Reset Types and Their Handling
- **Synchronous Reset**: Preferred in certain architectures like Xilinx FPGAs for better control and timing, but requires a clock signal.
- **Asynchronous Reset**: Widely used due to its ability to operate independently of the clock signal, making it suitable for low-power states and initial system startup.

## Challenges with Asynchronous Resets
- **Distribution**: Needs careful handling to avoid high fan-out and synchronization issues.
- **Noise Sensitivity**: Susceptible to noise, which can cause spurious resets.

## Multi-Clock Domain Reset
- Discusses the complexities of managing reset signals across different clock domains within an SOC, emphasizing the need for proper synchronization to prevent system failures.

## Reset Domain Crossing (RDC)
- **Definition**: Occurs when the reset signals of launch and capture flip-flops are different, potentially leading to metastability.
- **Solutions**: Strategies to synchronize resets to avoid issues in multi-clock environments.

## Power-on Reset (POR)
- **Function**: Ensures that the SOC starts in a known state upon power-up by providing a stable reset signal until all internal voltages and clocks are stable.
- **Implementation Details**: Typically involves a circuit that monitors the supply voltage and triggers a reset until the system is stable.

## Practical Insights
- **Reset Implementation**: Best practices for implementing and distributing reset signals to minimize latency and ensure stability across the SOC.
- **Synchronizing Resets**: Techniques to synchronize reset signals effectively to prevent errors in data processing and system operations.

## Conclusion
Effective reset management is crucial for the reliability and performance of SOCs, requiring careful consideration of timing, synchronization, and system architecture to ensure robust operations.

# Clock in SOC Design

## Overview
This document explores various aspects of clock management in System on Chip (SOC) design, emphasizing glitch-free switching, clock gating, and handling asynchronous interfaces.

## Key Topics
- **Glitch-free Clock Switching**: Strategies to switch clocks without creating glitches.
- **Clock Gating**: Techniques to reduce power consumption and manage timing.
- **Asynchronous Interface**: Handling the interface between asynchronous and synchronous systems.
- **Cross Clock Domain (CDC)**: Managing clock domain crossings to prevent data corruption.
- **Clock Generation and Distribution**: Techniques for generating and distributing clock signals efficiently across the SOC.

## Glitch-free Clock Switching
- **Switching Unrelated Clock Sources**: Details the potential for glitches when switching and methods to mitigate these issues.
- **Protection Strategies**: Includes using flip-flops to stabilize clock signals during switching.

## Clock Gating
- **Purpose**: Reduces power consumption by stopping the clock in inactive parts of the SOC.
- **Techniques**: Use of AND/OR logic to control clock signals, ensuring minimal pulse distortion.

## Asynchronous Interface
- **Challenges**: Covers the difficulties in synchronizing asynchronous signals to the system clock.
- **Solutions**: Implementation of dual flip-flop synchronization to reduce the risk of metastability.

## Cross Clock Domain (CDC)
- **Risks**: Discusses the dangers of clock domain crossings, particularly the potential for metastability and data corruption.
- **Management**: Best practices for safely managing CDC, including proper synchronization techniques and signal integrity checks.

## Clock Generation and Distribution
- **Generation**: Methods to create stable and reliable clock signals using PLLs and other technologies.
- **Distribution**: Techniques for distributing the clock signal with minimal skew and phase delay across the SOC.

## Practical Insights
- **Reset Synchronization**: Ensures reliable operation by coordinating resets with clock signals.
- **CDC Verification**: Methods to verify that clock domain crossings are handled correctly to prevent runtime errors.

## Conclusion
Effective clock management is critical for SOC performance and reliability. It involves careful planning of clock generation, gating, and distribution to meet the stringent requirements of modern electronics.

# Chip Design Flow Overview

## Introduction
This document outlines the comprehensive chip design flow for advanced SOC design, detailing the steps from initial concept through to sign-off.

## Key Stages of Chip Design

### Design Flow Overview
- **Initial Specification**: Establishes design requirements and goals.
- **RTL Design and Verification**: Involves writing and testing the RTL code using tools like VCS and Formality.
- **Synthesis**: Converts RTL to a gate-level netlist using Synopsys Design Compiler.

### Front-end Design
- **Simulation**: Uses VCS for simulating the RTL to verify logic and functionality.
- **Logic Synthesis**: Transforms RTL into a gate-level representation while optimizing the circuit.
- **Design for Test (DFT)**: Incorporates testability features into the hardware design.

### Backend Design - Physical Synthesis
- **Floorplanning**: Establishes the physical layout of the chip, including placement of cells and routing.
- **Placement and Routing**: Detailed placement of components and interconnect routing using tools like IC Compiler II.
- **Post-Layout Verification**: Involves checking the design against manufacturing rules and verifying the layout matches the schematic.

### Signoff
- **Static Timing Analysis (STA)**: Ensures the design meets all timing requirements using tools like PrimeTime.
- **Signal Integrity Analysis**: Checks for issues like crosstalk and noise.
- **Power Integrity Analysis**: Ensures reliable power distribution across the chip.

## Tools and Technologies
- **Synopsys VCS**: Used for RTL simulation.
- **Design Compiler**: For synthesis and optimization.
- **IC Compiler II**: Used for physical design tasks like placement and routing.
- **PrimeTime**: Employed for final signoff STA and power analysis.

## Detailed Processes
- **Physical Verification**: Checks for design rule violations and other manufacturability issues.
- **Parasitic Extraction**: Estimates the effect of parasitics on circuit performance.
- **Reliability Analysis**: Examines potential reliability issues, including electromigration and thermal effects.

## Conclusion
The chip design flow is a complex but structured approach that involves multiple stages and tools, each crucial for ensuring the final product meets its specified performance, power, and area targets.



# FSIC Architecture & Design

## Overview
The FSIC (Full-Stack IC) architecture is designed to implement an IC validation system based on the Caravel SOC, primarily for educational purposes in SOC design courses.

## Key Components
- **FSIC Architecture**: Utilizes the Caravel SOC for a hands-on approach in training various disciplines including IC design, FPGA design, and embedded programming.
- **FSIC-AXIS Interface Specification**: Details the interface specifications for handling AXI Stream connections and transactions between the FPGA and the SOC.
- **System Clocking Scheme**: Describes synchronous and source-synchronous clocking setups for reliable operation.
- **Module Specification**: Outlines the modules and their functionalities within the FSIC architecture.

## FSIC-AXIS Interface Specification
- **Axilite Overload**: Extension of the Axis specification to include configurations for downstream and upstream transactions.
- **Data Payload**: Handling for Axis transactions, ensuring proper data flow between the FPGA and the SOC.

## System Clocking Scheme
- Ensures that the FPGA and Caravel SOC operate synchronously, minimizing clock skew through careful layout and buffer management.

## Detailed Module Descriptions
- **User Project Wrapper**: Encapsulates user logic within the FSIC system, linking with the Caravel SOC.
- **AXILite-AXIS (AA)**: Handles protocol conversion between AXILite and AXIS, facilitating communication and configuration across different parts of the system.
- **IO_SERDES (IS)**: Manages IO serialization and deserialization to effectively increase the number of usable IO pins relative to the core clock.
- **Logic Analyzer**: Monitors and logs specific signals within the SOC for debugging and validation purposes.
- **AXIS Switch (AS)**: Manages data routing and protocol handling between different modules and external interfaces.

## Integration and Testing
- The architecture supports various testing and initialization sequences to ensure robust and reliable SOC operation from power-on to execution.

## Conclusion
The FSIC architecture provides a comprehensive framework for developing and testing SOC designs, with a strong emphasis on educational applications and practical, real-world system validation.


