NCKU DSP Arch NOTE
contributed by <yanjiun
>
課程:VLSI design for digital communication systems -N2109 of NCKU
學生:顏君翰 MS student
指導老師:謝明德 PhD
Retiming (請假)
- 目標:
- Clock period miniretiming
- Registers minimization (Linear Problem)
- 特性:
- Retiming dose not alter the iteration bound in a DFG
- Retiming 使用 Shortest Path Algorithm 解 constrains graph 得出
- Constrains 有三種
- feasible constrains : 不能讓邊上變負的。(必須)
- period constrains : 增加最大延遲條件。(通常會加上,需使用合理時間)
- registers constrains : 增加某點的fanout條件。(使問題變成線性規劃問題,解題複雜度大幅提升,斟酌使用)
- 如要使用需要最先使用 registers constrains,再算後續條件。
Demo
- 對以下電路實作完整 Retiming
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- feasible constrains
- Registers constrains
- Period constrains
Fesaible constrains (origin DFG)
轉換為 DFG 表示法。
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Registers minimization (add dummy node and breath )
增加虛擬點在要限制暫存器之 fanout
- 限制點
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Clock period constrains (computing and )
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- 限制最長延遲
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- 加上原圖
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使用 Shortest path algorithm 求解
- 並且最小化 COST
ILP Algorithm
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Definations
- : Original DFG, : Retimed DFG
- : Delay transferred from outgoing edges of node V to the incident deges of node V.
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: weigth(delay) of the edge
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: weight(delay) of the dege after retiming.
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after retiming has a weight of
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weighty of path
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path computaion time
Minimium clock period
Minimium registers
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- non-linear function, need reformulate.
Reformulate graph
- add a dummy node to
- : with no computing time.
- , where 是 邊中最大的延遲
- : 原本點有條邊,每條邊則為條
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- Registers constrains
- Minimium the
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介紹
forward cutsets retiming(pipeline) < cutsets retiming < retiming
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Retiming
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Cutset retiming rules
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forward cutsets retiming(pipeline)
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DFG
Replace each delay in a DFG with N delays.
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- Retiming 2-slow Graph

Shortest Path Algorithm
Floyd-Warshall algorithm
如果沒有負圈,就會找到最短路徑
- Initial frist matrix by DFG