* **combinational : An operational element, such as an AND gate or an ALU.**

* **state element : A memory element, such as a register or a memory.**
* **clocking methodology : THe approach used to determine when data is valid and stable relative to the clock.**
* **edge-triggered : clocking A clocking scheme in which all state changes occur on a clock edge.**
* **control signal : A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit.**
* **asserted : The signal is logically high or true.**
* **deasserted : the signal is logically low or false.**
* **datapath element : A unit used to operate on or hold data within a processor. In the MIPS implementation, the datapath elements include the instruction and data memories, the register file, the ALU, and adders.**
* **program counter (PC) : the register containing the address of the instruction in the program being executed.**
* **register file : A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.**
* **sign-extend : To increase the size of a data item by replicating the high-order sign bit of the original data item in the high order bits of the larger, destination data item.**
* **branch target address : the address speciled in a branch, which becomes the new program counter (PC) if the branch is taken. In the MIPS architecture the branch target is given by the sum of the offset field of the instruction and the address of the instruction following the branch.**
* **branch taken : A branch where the branch condition is satisfiled and the program counter (PC) becomes the branch target.Allunconditional jumps are taken branches.**
* **branch not taken or (untaken branch) : A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch.**
* **branch : A type of branch where the instruction immediately following the branch is always executed, independent of whether the branch condition is true or false.**
* **truth table : From logic, a representation of a logical operation by listing all the values of the inputs and then in each case showing what the resulting outputs should be.**
* **don’t-care term : An element of a logical function in which the output does not depend on the values of all the inputs. Don’t-care terms may be specified in different ways.**
* **opcode : the field that denotes the operation and format of an instructional designer.**
* **structural hazard : When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.**
* **data hazard : Also called a pipeline data hazard. When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available.**
* **forwarding : Also called bypassing. A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer visible registers or memory.**
* **single-cycle : implementation Also called single clock cycle implementation. An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical.**
* **pipelining : An implementation technique in which multiple instructions are overlapped in execution, much like an assembly line.**
* **load-use data hazard : A speci# c form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction.**
* **pipeline stall : Also called bubble. A stall initiated in order to resolve a hazard**
* **control hazard : Also called branch hazard. When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the ow of instruction addresses is not what the pipeline expected**
* **branch prediction : A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome**
* **latency (pipeline) : the number of stages in a pipeline or the number of stages between two instructions during execution.**
* **nop : An instruction that does no operation to change state.**
* **flush : To discard instructions in a pipeline, usually due to an
unexpected event.**
* **dynamic branch : prediction Prediction of branches at runtime using runtime information**
* **branch prediction : butter Also called branch history table. A small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently taken or not.**
* **branch delay slot : the slot directly after a delayed branch instruction, which in the MIPS architecture is filled by an instruction that does not affect the branch.**
* **Branch target buffer : A structure that caches the destination Program Counter PC or destination instruction for a branch. It is usually organized as a cache with tags, making it more costly than a simple prediction buffer.**
* **Correlating predictor : A branch predictor that combines the local behavior of a particular branch and global information about the behavior of some recent number of executed branches.**
* **Tournament branch predictor : A branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch.**
* **Exception : Also called an interrupt. An unscheduled event that disrupts program execution; used to detect overflow.**
* **Interrupt : An exception that comes from outside of the processor. (Some architectures use the term interrupt for all exceptions.)**
* **Vectored interrupt : An interrupt for which the address to which control is transferred is determined by the cause of the exception.**
* **Imprecise interrupt : Also called imprecise exception. Interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception.**
* **Precise interrupt : Also called precise exception. An interrupt or exception that is always associated with the correct instruction in pipelined computers.**
* **Instruction-level parallelism : The parallelism among instructions.**
* **Multiple issue : A scheme whereby multiple instructions are launched in one clock cycle.**
* **Static multiple issue : An approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution.**
* **Dynamic multiple issue : An approach to implementing a multiple-issue processor where many decisions are made during execution by the processor.**
* **Issue slots : The positions from which instructions could issue in a given clock cycle; by analogy, these correspond to positions at the starting blocks for a sprint.**
* **Speculation : An approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.**
* **Issue packet : The set of instructions that issues together in one clock cycle; the packet may be determined statically by the compiler or dynamically by the processor.**
* **Very Long Instruction Word (VLIW) : A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields.**
* **use latency : Number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline**
* **Loop unrolling : A technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are.**
* **Register renaming : The renaming of registers by the compiler or hardware to remove antidependences.**
* **Antidependence : Also called name dependence. An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions.**
* **Superscalar : An advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution.**
* **Dynamic pipeline scheduling : Hardware support for reordering the order of instruction execution so as to avoid stalls.**
* **Commit unit : The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer visible registers and memory.**
* **Reservation station : A buffer within a functional unit that holds the operands and the operation.**
* **Reorder buffer : The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register.**
* **Out-of-order execution : A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait.**
* **In-order commit : A commit in which the results of pipelined execution are written to the programmer visible state in the same order that instructions are fetched.**
* **Microarchitecture : The organization of the processor, including the major functional units, their interconnection, and control.**
* **Architectural registers : The instruction set of visible registers of a processor; for example, in MIPS, these are the 32 integer and 16 floating point registers.**
* **Instruction latency : Inherent execution time for an instruction.**