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# 計算機組織 預習筆記ch3

:::info
學號: B112040003
系級: 資工115
姓名: 張景旭
:::

## 3.1 introduction
* ### How to represent fractions and real num
* ### overflow
* ### How hardeware mutiply and divide

## 3.2 addition and subtraction
* ### addition: add it directly
* ### subtraction: do two's complement for the second one and do the adddition

* ### overflow

## 3.3 multiplication
* ### multiplicand: the first oprend
* ### mupliplier: the second oprend

* ### step
1. initial values
2. prod += Mcand
3. shift left Mcand
4. shift right Multoplier
5. repeat 2~4
## 3.4 division
* ### Dividend = Quotient $\times$ Divisor + Remainder

* ### Step
1. Initial values
2. Rem -= div
3. Rem < 0 $\Rightarrow$ +div,sll Q,Q0 =0, Rem $\geq0 \Rightarrow$ sll Q, Q0 = 1
4. shift Div right
5. repeat 2~4

## 3.5 floating-point

* ### represetation(IEEE 754): $(-1)^S \times F \times 2^E$
* expoent: $2^E$
* fraction: 1.xxxxxxx
* s: $(-1)^s$

* ### Step of addition

1. Compare the exponents of the two numbers;(shift the smaller number to the right until its exponent would match the larger exponent)
2. Add the significands
3. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent
4. checking if overflow

5. Round the significand to the appropriate

6. repeat 3.~5. until normalized
* ### step of multiplication

1. Add the biased exponents of the two numbers, subtracting the bias from the sum to get the new biased exponent
2. Multiply the significands
3. Normalize the product if necessary, shifting it right and incrementing the exponent
4. checking overflow
5. Round the significand to the appropriate number of bits

6. repeat 3.~5. until normalized
7. Set the sign of the product to positive if the signs of the original operands are the same; if they differ make the sign negative
* ### MIPS

## 3.6 Subword Parallelism
* ### A processor could use parallelism to perform simultaneous operations on short vectors of sixteen 8-bit operands, eight 16-bit operands, four 32-bit operands, or two 64-bit operands
* ### The extensions are classifi ed as subword parallelism. It is also classifi ed under the more general name of data level parallelism. Th ey have been also called vector or SIMD, for single instruction, multiple data.
## 3.7
* ### the 16 floating-point registers for SSE2 are actually 128 bits wide
## 3.9 fallacies and pitfalls
* ### The MIPS instruction add immediate unsigned (addiu) sign-extends its 16-bit immediate field.
> add immediate unsigned (addiu) is used to add constants to
signed integers when we don’t care about overfl ow. MIPS has no subtract immediate instruction, and negative numbers need sign extension, so the MIPS architects decided to sign-extend the immediate field
* ### fallacy: right shift by n-bit is equal to divided by $2^n$ and left shift by n-bit is equal to multiple by $2^n$
> when the number to be operate is unsigned, the conclusion is ture.
> but when the number is signed, the conclusion is wrong.
> consider -5 divided by 4:
in 8-bit binary, -5 is 0b1111 1011. when -5 divided by 4, we expect the outcome shall be -1. but 0b1111 1011 >> 2 = 0b0011 1110 which is 62 instead, absoutely wrong.
maybe try shift with sign extend? 0b1111 1011 >> 2 = 0b1111 1110 which is -2, close, but still wrong.