EECS 151 Project Design Task List

# EECS 151 Project Design Task List ## Hardware | Task | Written | Tested | Integrated | Finished | | ------------- | ------- | ------ | ---------- | -------- | | ALU | Yes | Yes | Yes | Yes | | RegFile | Yes | Yes | Yes | Yes | | ImmGen | Yes | Yes | Yes | Yes | | BranchComp | Yes | Yes | Yes | Yes | | Load Extend | Yes | Yes | Yes | Yes | | Control Logic | Kind of | Yes | Yes | Yes | | Mux modules | Yes | Yes | Yes | Yes | | CSR Registers | Yes | N/A | Yes | Yes | | Memory | Yes | Yes | Yes | Yes | | Cycle Counter | Yes | Yes | Yes | Yes | | Instruction Counter | Yes | Yes | Yes | Yes | | NOP Injection Logic | Yes | Yes | Yes | Yes | ## Software - [x] Randomized benchmark testing ## Control Logic ### Instruction Fetch - `PCSel`: standard, choose between: `PC` (nop), `ALU`, `PC+4`, `jal_jalr_mux_fwrd` - `JSel`: this is for when we forward the output of RegFile backwards and avoid a stall on jumps: selections whether we are forwarding data from `JAL` or `JALR` - `bios_ena`: enable BIOS memory read: (Note: IMEM doesn't have any similar read enable signal in IF) ### Instruction Decode - `pc_ID[30]`: Selects between IMEM and BIOS for instructions, nothing needs to be done to implement this, just here for completeness ### Execute - `RS1Sel`: forwarding logic selection for the RS1 RegFile output - `RS2Sel`: forwarding logic selection for the RS2 RegFile output - `BrUn`: standard, check if register data should be compared: ned or signed based on inst - `CSRSel`: select the either register or immediate depending on CSR instruction type - `CSRWEn`: controls whether the value of the csr register can change or not - `ASel`: standard, check if we want `PC+4` or mux-processed `Reg[rs1]` - `BSel`: standard, check if we want `imm` or mux-processed `Reg[rs2]` - `ALUSel`: standard, check what computation ALU should do (almost always add) - `data_in_valid`: UART input for when the UART can read from CPU - `data_out_ready`: UART input for when the CPU is ready to read from UART - `bios_enb`: enable signal for BIOS memory - `dmem_en`: enable signal for DMEM memory - `dmem_we`: write enable signal for DMEM memory - `imem_ena`: enable signal for IMEM memory - `imem_wea`: write enable signal for IMEM memory - `InstCountEn`: enable the instruction counter ### Writeback - `RegWEn`: standard, check if we want to write signal back to RegFile based on inst, feeds into RegFile WEn port - `MEMSel`: selects between the different memories for use by load extend - `LDSel`: standard, check how we process the loaded word from memory (based on the inst being `lw`, `lh`, etc.) - `BYTESel`: determines where we are masking the memory output - `WBSel`: which data are we writing back ## Planning for Checkpoint 3: I/O Integration, PWM Controller, Subtractive Synthesizer ### List of All IO's: - Read: - UART control: `0x80000000` - UART receive data: `0x80000004` - Cycle counter: `0x80000010` - Instruction counter: `0x80000014` - GPIO FIFO empty: `0x80000020` - GPIO FIFO read data: `0x80000024` - Switches: `0x80000028` - TX acknowledge: `0x80000040` - Write: - Reset counters: `0x80000018` - UART transmitter data: `0x80000008` - GPIO LEDs: `0x80000030` - Duty cycle: `0x80000034` - TX request: `0x80000038` - Sine NCO scale: `0x80000200` - Square NCO scale: `0x80000204` - Triangle NCO scale: `0x80000208` - Sawtooth NCO scale: `0x8000020c` - Frequency control word (voice 1): `0x80001000` - Global gain shift: `0x80000104` - PWM DAC source: `0x80000044` - Global synth reset: `0x80000100` - Note start (voice 1): `0x80001004` - Note release (voice 1): `0x80001008` - Note finished (voice 1): `0x8000100c` - Reset (voice 1): `0x80001010` - Frequency control word (voice 2): `0x80002000` - Note start (voice 2): `0x80002004` - Note release (voice 2): `0x80002008` - Note finished (voice 2): `0x8000200c` - Reset (voice 2): `0x80002010` ### `io_mmap` Module #### Purpose - organize the functionality of all memory related operations (those remnant from checkpoint 2, and the additional I/O content from checkpoint 3. - simplify `Risv151.v` with fewer modules, make things more block-level, reduce clutter/expansiveness of control_logic.v, ease of isolating critical path (when the time comes to up `CLK_FREQ` to `100 Mhz`). #### Inputs and Outputs (`parameter`s not included) - Inputs for Cycle Counter - `.clk()`, `.rst()`, `.CounterReset()` - Outputs for Cycle Counter - `.count()` - Inputs for Instruction Counter - `.clk()`, `.rst()`, `.CounterReset()`, `.InstCountEn()` (make sure instruction counter is only incremented on 'actual' instructions) - Outputs for Instruction Counter - `.count()` - Inputs for UART - `.clk()`, `.reset()`, `.data_in()`, `.data_in_valid()`, `.data_out_ready()`, `.serial_in()` - Outputs for UART - `.data_in_ready()`, `.data_out()`, `.data_out_valid()`, `.serial_out()` #### Controls/Outputs - Control Signals: - #### What this Includes - logic for using the memory address to properly handle each operation - includes the cycle counter, instruction counter, and UART inputs: all signals needed by UART, instruction counter, cycle counter outputs: