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# System prepended metadata

title: SOCStudy.md

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---
title: 'SoC Lab Study Notes'
disqus: hackmd
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# SoC Lab Study Notes

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[TOC]

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# Lab_1 
<!-- >[time=Sat, Sep 16, 2023 10:23 PM] -->
## Intro
* In this lab, we implemented a simple multiplier as the entire system. The system takes two 32-bit signed integers as inputs. The primary objective of this lab is to familiarize ourselves with the workflow of using these design tools.

## Others
* In linux, command to choose a specific disk
```gherkin=
sudo fdisk <disk_location>
```
---
# Lab_2 
<!-- >[time=Sun, Sep 17, 2023 9:12 PM] -->
## Intro
* In this lab , we've developed a Finite Impulse Response (FIR) filter. Our systemtakes two sets of 32 bit signed integers as inputs: 'pn32HPInput' for data and'an32Coef' for filter coefficients. Then we use shift registers to manage past inputvalues and accumulate the filtered output in 'pn32HPOutput.'

* Furthermore, we have designed the project with two interfaces
    * (1) AXI Lite interfaces
    * (2) AXI Stream interfaces

## Difference of AXI_Master and Stream interfaces
* **AXI_Master** :  Ideal for complex data transfers, especially for <font color="#00f">memory and peripherals requiring structured</font>, transaction-based communication. Provides strong control and adaptability.
* **Stream** : Perfect for <font color="#00f">continuous data flow</font> applications with low latency needs. Excellent for real-time tasks like video and audio processing, ensuring immediate, uninterrupted data processing.

## Others
* In linux, check whether two files are the same 
```gherkin=
if (system("diff <file1_name> <file2_name>")) {
    cout << ">> Test failed!" << endl;
    return 1;
}
```

* Co-simulation failed 
    * Due to depth settings of interfaces
[Lab2 - Error when running co-simulation #53](https://github.com/bol-edu/HLS-SOC-Discussions/discussions/53#discussioncomment-7045125)
![](https://hackmd.io/_uploads/Byf1zkOka.png)

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# Lab_3 
## Intro
* In this lab, we implemented a FIR system in Verilog, using AXI-Lite interfaces for coefficients and Stream interfaces for data. We also collaborated with a BRAM module to handle data efficiently. The core focus of this lab is to master the control of handshake signals within these protocols and to create a well-designed data flow.

## System Block Diagram

![image](https://hackmd.io/_uploads/B1Ag_0QKp.png)

![image](https://hackmd.io/_uploads/rJRHuRQKa.png)

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# Lab_4
## Intro
* In lab4-1, we use the firmware code to implement the FIR engine, and we build up the interface of wishbone and user bram. In lab4-2, we use the FIR.v design in lab3 to do filtering rather than using the firmware code. On the other hand, we use firmware code to control the dataflow.

* Two main tasks we’ve done : 
    * (1) Modify FIR.v to communicate with the WB successfully
    * (2) Wrap and merge WB-AXI decoder, FIR and the     original file in user_proj_example.counter.v
    * (3) Define the new MMIO address for user project in caravel.h
    * (4) Modify the testbench (counter_la_fir_tb.v) to print the received data Y and the timer.

## Wishbone user-defined address map


| User-defined Signals |    Address    |
|:--------------------:|   :-------:   |
|      ap signals      |  0x38001000   |
|     data length      |  0x38001010   |
|     coefficient      |  0x38001020   |
|     stream data      |  0x38002000   |
|    "last" signal     |  0x38002008   |


## System Block Diagram
![image](https://hackmd.io/_uploads/rJty5CXKp.png)

---

# Lab_5
## Intro
* In this lab, we put the Caravel SoC simulation environment into FPGA board and connect three IPs with the SoC: caravel_ps, read_romcode and output_pin. We use Jupyter Notebook to validate the simulation result.

## System Block Diagram
![image](https://hackmd.io/_uploads/SJXrsAXYa.png)

![image](https://hackmd.io/_uploads/Bkqxa07Ya.png)


---

# Lab_6
## Intro
* In Lab6, we integrate the four workloads by modify the firmware code and the testbench. We also add a decoder in user project hardware to separate the user project and the uart request. After integrated the workloads, we synthesis and implement the design and use jupyter notebook to verify the results.

* Four workloads in the lab  : 
    * (1) Matrix multiplication
    * (2) Quick Sort
    * (3) FIR
    * (4) UART

## System Block Diagram
![image](https://hackmd.io/_uploads/BJ_osCmFa.png)

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# Lab_SDRAM
## Intro
* We replace the BRAM with SDRAM to store the data and the firmware code.
* Three tasks in this lab  : 

    * (1) replace the adder with matrix multiplier
    * (2) add the prefetch function in SDRAM controller
    * (3) separate data and firmware into two banks in SDRAM

## System Block Diagram
![image](https://hackmd.io/_uploads/BJ_osCmFa.png)

## SDRAM Interface
* SDRAM interface contain: sdram_cle, sdram_cs, sdram_cas, sdram_ras, sdram_we, sdram_dqm, sdram_ba, sdram_a (address), sdram_dqi (input data), sdram_dqo (output data). The interface is controlled by the sdram controller.

## SDRAM Controller
* SDRAM controller is controlled by the user interface, and the controller will send the address to sdram to fetch or write the data. There’s an FSM in the controller:

![image](https://hackmd.io/_uploads/H1GuhC7Fp.png)

![image](https://hackmd.io/_uploads/H1It3AmKT.png)

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