--- title: Lab3 RV32I tags: RISCV --- * 環境變數 ```c= $ export CROSS_COMPILE=riscv-none-elf- ``` ```c= $ cd verilator $ export VERILATOR_ROOT=`pwd` ``` ```c= export VERILATOR_ROOT=$HOME/verilator export PATH=$VERILATOR_ROOT/bin:$PATH ``` ```c= $ cd xpacks/xpack-dev-tools-riscv-none-embed-gcc/.content/bin $ pwd -> 為以下輸入 $ export PATH=$PATH:/home/will/srv32/xpacks/xpack-dev-tools-riscv-none-embed-gcc/.content/bin ``` #### Installation * According to README.md from [SRV32 - Simple 3-stage pipeline RISC-V processor](https://github.com/sysprog21/srv32), I install RISC-V toolchain via pre-built GNU Toolchain [xPack GNU RISC-V Embedded GCC v10.2.0-1.2](https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/tag/v10.2.0-1.2) * follow the [tutorial](https://hackmd.io/@eecheng/B1fEgnQwF) * SRV32 - Simple 3-stage pipeline RISC-V processor ```c= $ cd ~ $ git clone https://github.com/sysprog21/srv32.git ``` #### C program & Compilation * [HW1: 268. Missing Number](https://hackmd.io/RZZjDN1ySteVXBPMDUzicQ?view) ```c= #include<stdio.h> int missingNumber(const int*, const int); int main() { const int nums[] = {3, 0, 1}; const int numsSize = 3; printf("%d\n", missingNumber(nums, numsSize)); return 0; } int missingNumber(const int* nums, const int numsSize) { int ans = numsSize; for (int i = 0; i < numsSize; ++i) { ans ^= i ^ nums[i]; } return ans; } ``` * Create directory for C program and Makefile * Run the ISS sim ```c= Excuting 1245 instructions, 1599 cycles, 1.284 CPI Program terminate Simulation statistics ===================== Simulation time : 0.001 s Simulation cycles: 1599 Simulation speed : 1.307 MHz ``` * Run the RTL sim ```c= Excuting 1245 instructions, 1599 cycles, 1.284 CPI Program terminate - ../rtl/../testbench/testbench.v:434: Verilog $finish Simulation statistics ===================== Simulation time : 0.039 s Simulation cycles: 1610 Simulation speed : 0.0412821 MHz ```