# 軟硬體協同 HW1

(Excess-3/Decimal) to 7-Seg Display with Preset/Reset
7 segment display:
Truth tabel:

7-segment display table:

Verilog code:

module seg7 (
    input [3:0] in,
    input       ex3, reset_n, preset,
    output reg [7:0] out
);
    wire [3:0] in_p3; //four bits in + decimal 3 without carry
    wire       carry; //detecting overflow in excess-3 mode 
    assign {carry, in_p3[3:0]} = in[3:0] + 4'd3;

    wire [3:0] bts_in; //bin-to-7segment input
    assign bts_in[3:0] = (ex3)? in_p3[3:0]:in[3:0];

always @(*) begin
    if(~reset_n) begin
        out = 8'b11010101;
    end
    else if(preset) begin
        out = 8'b00110001;
    end
    else if(ex3 && carry) begin
        out = 8'b11111101;
    end
    else begin
        case(bts_in) 
        4'h0: out = 8'b00000011;
        4'h1: out = 8'b10011111;
        4'h2: out = 8'b00100101;
        4'h3: out = 8'b00001101;
        4'h4: out = 8'b10011001;
        4'h5: out = 8'b01001001;
        4'h6: out = 8'b01000001;
        4'h7: out = 8'b00011111;
        4'h8: out = 8'b00000001;
        4'h9: out = 8'b00001001;
        4'hA: out = 8'b00010001;
        4'hB: out = 8'b11000001;
        4'hC: out = 8'b01100011;
        4'hD: out = 8'b10000101;
        4'hE: out = 8'b01100001;
        4'hF: out = 8'b01110001;
        default: out = 8'd0; //theoretically there is no condition left
        endcase
    end
end

endmodule

schematic:

testbench

`timescale 1ns/1ns
module seg7_tb;
reg [3:0] in;
reg ex3, reset_n, preset;
wire [7:0] out;

seg7 seg7( .in(in), .ex3(ex3), .reset_n(reset_n), .preset(preset), .out(out) );

initial begin
    #0 in[3:0] = 4'd0;
    #0 ex3=0; reset_n=1; preset=0;
    //normal operation

    #160 ex3=1; 
    //excess 3 operation

    #160 ex3=0; reset_n=0; preset=0;
    #20  ex3=0; reset_n=1; preset=1;
    #10  ex3=0; reset_n=0; preset=1;

    #30  ex3=1; reset_n=0; preset=0;
    #10  ex3=1; reset_n=1; preset=1; 
    #20  ex3=1; reset_n=0; preset=1;

    #20 $finish;
end

always begin
    #10 in[3:0] = in[3:0] + 1'd1;
end

endmodule

Simulation result:

The implementation on FPGA is successful. Here is some picture:
in=0000, reset_n=1, preset=0, ex3=0

in=1001, reset_n=1, preset=0, ex3=0

in=0000, reset_n=0, preset=0, ex3=0 (reset mode)

in=0000, reset_n=1, preset=1, ex3=0 (preset mode)

in=0000, reset_n=1, preset=0, ex3=1 (excess-3 mode)

I do try all combination of input signals, but for simplicity, I only upload few pictures.