# Assignment 1: RISC-V Assembly and Instruction Pipeline ## Problems B My first attmpt is by just translate the `clz` function C code into assembly code. ```asm clz: li a1, 32 li a2, 16 clz_loop: srl a3, a0, a2 beq a3, zero, clz_cond sub a1, a1, a2 mv a0, a1 clz_cond: srli a2, a2, 1 bne a2, zero, clz_loop clz_ret: sub a1, a1, a0 ret ``` The upper 4 bits represent the exponent (e), which determines the number's offset and step size. The lower 4 bits are the mantissa. The mantissa is multiplied by the step size, which is calculated from the exponent as $2^e$. The offset is calculated using the formula $(2^e−1) \cdot 16$. This decode function takes 13 clock cycles to execute on a 5-stage processor. ```asm decode_uf8: andi a1, a0, 0xf srli a2, a0, 4 li a3, 0x7fff li a4, 15 sub a4, a4, a2 srl a3, a3, a4 slli a3, a3, 4 sll a1, a1, a2 add a1, a1, a3 ret ``` Inside encoding function. First just translate the C code into assembly. ```asm encode_uf8: addi a2, zero, 16 add a4, a0, zero add a1, a0, zero blt a0, a2, euf8_ret add a5, ra, zero jal ra, clz add ra, a5, zero addi a2, zero, 31 sub a1, a2, a1 addi a2, zero, 5 add a3, zero, zero add a0, a4, zero add a4, zero, zero blt a1, a2, euf8_exp_loop addi a2, zero, 4 sub a3, a1, a2 addi a5, zero, 15 add a2, zero, zero blt a3, a5, euf8_overflow_loop add a3, a5, zero euf8_overflow_loop: bge a2, a3, euf8_adj_loop slli a4, a4, 1 addi a4, a4, 16 addi a2, a2, 1 jal zero, euf8_overflow_loop euf8_adj_loop: beq a3, zero, euf8_exp_loop bge a0, a4, euf8_exp_loop addi a5, zero, 16 sub a4, a4, a5 srli a4, a4, 1 addi a5, zero, 1 sub a3, a3, a5 jal zero, euf8_adj_loop euf8_exp_loop: addi a5, zero, 15 bge a3, a5, euf8_ret slli a5, a4, 1 addi a5, a5, 16 bge a0, a5, euf8_ret add a4, a5, zero addi a3, a3, 1 euf8_ret: sub a1, a0, a3 srl a1, a1, a3 slli a3, a3, 4 or a1, a1, a3 ret ```