**期中報告** 32bit除法器 將被除數擴充成64bit,每次將被除數和除數進行比較,若大於除數,將被除數前32bit減去除數,並將被除數+1,若小於除數,則甚麼都不做,執行32次,被除數前32bit為餘數,後32bit為商。 ```verilog= module division32 ( input[31:0] A, input[31:0] B, output[31:0] quotient, output[31:0] remainder ); reg[31:0] tempA; reg[31:0] tempB; reg[63:0] temp_a; reg[63:0] temp_b; integer i; always @(a or b) begin tempA <=A; tempB <=B; end always @(tempA or tempB) begin temp_a = {32'h00000000,tempA}; temp_b = {tempB,32'h00000000}; for(i=0;i<32;i=i+1) begin temp_a = {temp_a[62:0],1'b0}; if(temp_a[63:32]>=tempb) temp_a = temp_a-temp_b +1'b1; else temp_a = temp_a; end quotient <=temp_a[31:0]; remainder <=temp_a[63:32]; end endmodule ``` 32bit 乘法器 利用如上圖所示的方法,一次對一個bit進行判斷,執行32次,再將用於判斷的數右移一個bit,完成迴圈即是答案。 ```verilog= module mult32( input wire[31:0] a, input wire[31:0] b, output reg[63:0] ans ); reg[63:0] pv; reg[63:0] ap; integer i; always @() begin pv = 64'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; ap = {32'b0000_0000_0000_0000_0000_0000_0000_0000,a}; for(i=0;i<=31;i=i+1) begin if(b[i]==1) pv = pv+ap; ap = {ap[62:0],1'b0}; end ans = pv; end endmodule ```
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