module Generator_Test (
input clk, // 時鐘信號
input rst_n, // 重置信號，低有效
input [7:0] voltage_in, // 輸入電壓（0~255）
input [7:0] current_in, // 輸入電流（0~255）
output reg [7:0] voltage_out, // 測試後的電壓
output reg [7:0] current_out, // 測試後的電流
output reg voltage_alarm, // 電壓警報
output reg current_alarm, // 電流警報
output reg test_active // 測試啟動標誌
);

// 定義電壓與電流範圍
parameter VOLTAGE_MIN = 8'd50, // 最小電壓
VOLTAGE_MAX = 8'd220, // 最大電壓
CURRENT_MIN = 8'd10, // 最小電流
CURRENT_MAX = 8'd100; // 最大電流

// 測試狀態機
reg [1:0] state, next_state;
parameter IDLE = 2'd0, // 空閒狀態
TEST_RUNNING = 2'd1, // 測試進行中
TEST_FINISHED = 2'd2; // 測試完成

// 狀態機：當 clk 或 rst_n 變化時更新當前狀態
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end

// 決定下一狀態：測試啟動與結束
always @(*) begin
case(state)
IDLE: begin
if (voltage_in > 0 && current_in > 0)
next_state = TEST_RUNNING; // 當電壓電流有效時，開始測試
else
next_state = IDLE;
end

TEST_RUNNING: begin
next_state = TEST_FINISHED;
end

TEST_FINISHED: begin
if (voltage_in == 0 || current_in == 0)
next_state = IDLE; // 停止測試
else
next_state = TEST_FINISHED;
end

default: next_state = IDLE;
endcase
end

// 輸出控制與警報設定
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
test_active <= 0;
voltage_alarm <= 0;
current_alarm <= 0;
voltage_out <= 8'd0;
current_out <= 8'd0;
end else begin
case(state)
IDLE: begin
test_active <= 0;
voltage_alarm <= 0;
current_alarm <= 0;
voltage_out <= 8'd0;
current_out <= 8'd0;
end

TEST_RUNNING: begin
test_active <= 1;

// 設定輸出電壓與電流
voltage_out <= voltage_in;
current_out <= current_in;

// 驗證電壓範圍
if (voltage_in < VOLTAGE_MIN || voltage_in > VOLTAGE_MAX)
voltage_alarm <= 1; // 電壓異常
else
voltage_alarm <= 0;

// 驗證電流範圍
if (current_in < CURRENT_MIN || current_in > CURRENT_MAX)
current_alarm <= 1; // 電流異常
else
current_alarm <= 0;
end

TEST_FINISHED: begin
test_active <= 0;
end
endcase
end
end

endmodule