[TOC]

# Vic

# W414

## Rule:
- **W414-Reports non-blocking assignment in a combinational block**

## When to Use:
- Use the rule to identify `non-blocking` assignments in a combinational block.

## Potential Issues:
- Violations may arise when a `non-blocking` assignment is used in a combinatonal block.

## How to Debug and Fix:
- Double-click the violation message. The HDL Viewer window highlights the line where the `non-blocking` assignment is used for the specific signal.
- To fix this problem, use only `blocking` assignments in combinational blocks.

## Example Code:

module group3(set, reset, vic, lukas);
    input set, reset;
    output vic, lukas;
    reg vic, lukas;

    always @(posedge vic) begin
    	lukas <= set;
    end

    always @(set or reset) begin
    	vic <= set & reset; // non-blocking assignments is used in a combinational always block.
    	lukas <= set | reset;
    end

endmodule

# W446

## Rule:
- **W446-Output port signal is being read (within the module)**

## Potential Issues:
- The W446 rule flags output ports that are read in the module where they are set.
- Such modules could lead to a unintended feedback path from the instantiating module in the post-synthesis simulation while this issue is not apperent in the pre-synthesis simulation.

## How to Debug and Fix:
- Such models are not recommended for some test tools that need to handle `inout` ports specially.

## Example Code:

module group3(
    input in1,
    input in2,
    output reg out, 
    output reg feedback
    );

    assign out = in1 & in2; // The output "out" is read in the design instead of setting it.
    assign feedback = out | in2; 

endmodule

* We cannot drive or `assign` `reg` type variables with an `assign` statement because a `reg` variable is capable of storing data and is not driven continuously. Reg signals can only be driven in procedural blocks such as `always` and `initial`.

# W505

## Rule:
- **W505-Ensure that the signals or variables have consistent value.**

## When to Use:
- Use this rule to identify the signals or variables that are assigned values using both blocking and non-blocking assignments.

## Potential Issues:
- The violation is reported arise when a variable or a signal is assigned in both blocking and non-blocking manner.

## How to Debug and Fix:
- The following message appears at the location where a signal or variable `<name>` is being assigned in a non-blocking(blocking) mode:

[WARNING] Variable/Signal '<name>' is being assigned in both blocking and nonblocking manner.

- Double-click the violation message. The HDL Viewer window will highlights the line, where a signal or a variable is again assigned a value or again using the blocking or non-blocking assignment and the previous assignment to that signal was done through non-blocking/blocking assignment.
- To fix the violation, ensure that all assignments to the same signal or variable are made in a consistent manner.

## Example Code:

reg [3:0] kenny;

kenny <= 1;
kenny = 2; 
// kenny is assigned using both blocking and nonblocking assignments. 
// Hence, a violation is reported in the case.

# Function/Task

| Function | Task |
| -------- | -------- |
| Can**not** have time-controlling statements-delay, and hence executes in the same simulation time unit | Can contain time-controlling statement/delay and may only complete at some other time |
| Can**not** enable a task, because of the above rule | Can enable othertasks and functions |
| Should have at least one input argument and cannot have **output** or **inout** arguments | Can have zero or more arguments of any type |
| Can return only a **single value** | Can**not** return a value, but can achieve the same effect using **output** argument |

# Example of Function:

function [7:0] bcd2ssd;
    input [3:0] bcd;
    begin
    case(bcd)
    4'd0: bcd2ssd = 8'b00000011;    //number 0
    4'd1: bcd2ssd = 8'b10011111;    //number 1
    4'd2: bcd2ssd = 8'b00100101;    //number 2
    4'd3: bcd2ssd = 8'b00001101;    //number 3
    4'd4: bcd2ssd = 8'b10011001;    //number 4
    4'd5: bcd2ssd = 8'b01001001;    //number 5
    4'd6: bcd2ssd = 8'b01000001;    //number 6
    4'd7: bcd2ssd = 8'b00011111;    //number 7
    4'd8: bcd2ssd = 8'b00000001;    //number 8
    4'd9: bcd2ssd = 8'b00001001;    //number 9
    endcase
    end
endfunction

# Example of Task:
1. Tasks can have any number of inputs and outputs
2. Tasks can have time delay `posedge, # delay, etc`
3. Tasks can call other tasks and functions
4. Tasks can drive global variables external to the task
5. Variables declared inside a task are local to that task
6. Tasks can use `non-blocking` and `blocking` assignments

module group3();
    reg [7:0] C8763    = 8'd0;
    reg       addr_vld = 1'b0;
    reg       data_vld = 1'b0;
    
    // Task can have time delay(posedge, #delay, etc)
    task MyNameIsVic;
        input [7:0] in_addr, in_data;
        begin
        // using external global reg
        addr_vld = 1'b1;
        C8763    = in_addr;
        #10; // 10 units of time delay
        addr_vld = 1'b0;
        data_vld = 1'b1;
        C8763    = in_data;
        #10;
        data_vld = 1'b0;
        #10;
        end
    endtask
    
    initial
    begin
        #10;
        MyNameIsVic(8'h10, 8'h0);
        MyNameIsVic(8'h18, 8'h1);
    end
    
endmodule

# W243

## Rule:
- **W243-Recursive task enable**

## Potential Issues:

- The W243 rule flags the task statement block, which has a call to task with the same name. It also reports a message, if a task call is recursive through more than one task. Ex: `task_0` calls `task_1` and `task_1` calls `task_0`.

## How to Debug and Fix:

- While it is true that in Verilog '95 we could not use recursion because the language did not support it, with Verilog 2001, recurison is possible. It is really useful for describing hardware that has a tree structure.
- In case of recursive task enable, there is always a chance that two tasks call each other infinitely. **Avoid** such situation by using loop constructs or some alternate method of writing the code.

## Example Code:

module group_3(
    input in1, 
    input in2, 
    output reg out1
    );
    
    always @(in1 or in2) begin
        MyNameIsVic(out1, in1, in2); // Recursive task calls
    end

    task MyNameIsVic;
        output o2;
        input in1, in2;
			
        begin
            MyNameIsVic( o2, in1, in2 ); // Recursive
        end
    endtask
    
endmodule

# W428

## Rule:
- **W428-Ensure that a task is not called inside a combinational block**

## When to Use:
- Use this rule to identify the tasks that are called inside a combinational block.

## Potential Issues:

- Since tasks may contain event controls, a task called inside a combinational `always` construct may turn that construct into a sequential `always` construct.
- Violation may arise when a task is called in a combinational block.

## How to Debug and Fix:

- Double-click the violation message. The HDL window highlights the location where a task call has been made inside a combinational always construct.
- To fix this violation, it is advisable to use functions, rather than tasks, inside combinational blocks.

## Example Code:

// No Violation, Task called from sequential block
always @(posedge clk) begin
    MyNameIsVic(in, out1);
end

// Violation, Task called from combinational block
always @(clk) begin
    MyNameIsVic(in, out1);
end

// Task
task MyNameIsVic;
    input in;
    output out1;
    begin
        <task body>
    end
endtask

# W429

## Rule:
- **W429-Task called in a sequential block**
## Potential Issues:
- Since tasks may contain event controls, a task called inside a sequential `always` construct may unexpectedly create an implicit state machine which may not be synthesizable if the task uses different edges or clocks from the block in which it is instanced. Therefore while it is not an error to call a task inside a sequential `always` block, it should be handled with an extra caution.

## How to Debug and Fix:
- Nothing to fix if this is done right, but does **suggest need for careful review**.

## Example Code:

module group3(in, out, clk);
    input [3:0] in;
    input clk;
    output [3:0] out;
    
    reg [3:0] out;
    reg [3:0] r1, r2, r3;
    
    always @(posedge clk) begin
        r1 = in - 1'b1;
        MyNameIsVic(r1, r2); // Call a task in sequential always construct
        out = r3;
    end
    
    task MyNameIsVic;
        <task_body>
    endtask
    
endmodule

# Lukas
# W287c
## Rule:
- **Inout port of an instance is not connected or connected net is hanging**
## Potential Issues:
- The W287c flags module or gate instances where inout ports are not connected or connected net is not used anywhere in the module.
- Such descriptions are allowed, they are generally design mistakes. When in the input mode, an unconnected inout port is equivalent to an undriven input which is a design error in CMOS unless it is a pull-up or pull-down.
## How to Debug and Fix:
- Tie the input high or low if it will not be used.
# W504
## Rule:
- **Integer is used in port expression**
## Potential Issues:
## How to Debug and Fix:
- Do not use integers in port expression. Pass integer to lower level module by parameters.
## Example Code:
- In the following example, the W504 rule reports violations because integer variable i and constant integer 2 are used in the expression of port a:

module m;
    integer i;
    mm1 u1(.a(i));
    mm1 u2(.a(2));
endmodule

module mm1(input a); 
endmodule

# badimplicitSM1
## Rule:
- **Identifies the sequential logic in a non-synthesizable modelling style where clock and reset cannot be inferred**
## Potential Issues:
- Violation may arise when uncommon sequential logic is used, which is unsynthesizable.
## How to Debug and Fix:
## Example Code:

module bism1(set,reset,in1,in2,out1);

input in1,in2,reset,set;
output out1;
reg clk,out1;
always @(posedge clk or negedge set)
    if(reset)
        out1 = 0; 
    else if(!set) 
        out1 = 1;
    else if(in2) 
        out1 = in2;
    else
        out1 = in1;
endmodule

# badimplicitSM2
## Rule:
- **Identifies the implicit sequential logic in a non-synthesizable modeling style where states are not updated on the same clock phase**
## Potential Issues:
- A register which is updated on both edges of a clock in a given sequential block leads to ambiguous synthesis results.
## How to Debug and Fix:
- To debug the violation, double-click the message. The HDL Viewer window highlights the line where switching on the second edge of the same clock is done. To confirm the implicit sequential logic using both clock phases, perform one of the following steps:
-- Inspect the block visually
-- Scroll up the HDL Viewer window to search for the always construct
-- Search the HDL for the edge of clock used in the if statement
- To resolve the violation, break the sequential logic into multiple sequential logic blocks, each of which can independently meet the requirement. If the register depends on both edges of the clock, describe the sequential nature separately and use the combinational logic to generate the final output.
## Example Code:
- In the following example code, SpyGlass generates a violation as the state depends on more than one edge of the clk clock:

module test(out1,out2); 
output out1,out2;
reg out1,out2,a,c,clk; 
always
    begin
        @(posedge clk) out1 <= c; @(negedge clk) out2 <= a;
    end 
endmodule

# badimplicitSM4
## Rule:
- **Identifies the non-synthesizable implicit sequential logic where event control expressions have multiple edges**
## Potential Issues:
- A violation is reported A register which is updated on both edges of a clock in a given sequential block leads to ambiguous synthesis results.
- The synthesis tool can get confused about which edge to use for updating the register.
- RTL and gate-level simulation results may not match.
## How to Debug and Fix:
- To resolve the violation, break the sequential logic into multiple sequential logic blocks, each of which can independently meet the requirement.

## Example Code:
- In the following example code, SpyGlass reports a violation as the event control expressions use multiple edges.

always 
    begin
        @(posedge a or negedge a) out1 <= in1;
        @(negedge a) out2 <= in1; 
    end
endmodule

# bothedges
## Rule:
- **Identifies the variable whose both the edges are used in an event control list**
## Potential Issues:
- A violation is reported when both edges of the same variable are used in an event control list, hence making the variable not synthesizable by some synthesis tools.
## How to Debug and Fix:
- To resolve the violation, replicate the block, one switching on the positive edge and the other on the negative edge.
## Example Code:

module test(q);

output q;
reg q,d,reset;

always @(posedge reset or negedge reset) 
  begin if (reset != 0) 
    q = d;
  end

# infiniteloop
## Rule:
- **While/forever loop has no break control**
## Potential Issues:

## How to Debug and Fix:
- Fix may not be necessary if this is expected to be free-running, but you should check each such case.
## Example Code:

`define cond 1'b1
module test(in1, in2, sel, out1); input in1, in2, sel;
    output out1;
    reg out1;
    always@(sel or in1) 
      while(`cond)         // here 
          case(sel)
              1'b0: out1 <= in1; 
              1'b1: out1 <= in2;
          endcase 
endmodule

# mixedsenselist
## Rule:
- **Mixed conditions in sensitivity list may not be synthesizable**
## Rule Description:
- The mixedsenselist rule flags mixed edge and non-edge conditions in the sensitivity list of an always construct.
- Such conditions in sensitivity list may not be synthesizable by some synthesis tools.
## How to Debug and fix it?
- Decide if you really want to trigger the block on any change in the mixed signal. Check if your requirement can be met by mapping to either a positive-edge change or a negative-edge change. If both are required, consider duplicating the block, one triggering on each edge.
## Example code:

always @(posedge clock or reset) 
    q = d;

- In this example, the always construct has both an edge specification and a non-edge specification:

# Kenny
# W416
## Rule:
- Width of return type and return value of a function should be same
## Potential issues (width mismatch)
- A violation is reported when the return type width is lesser or greater than the width of the return value of a function.
## How to Debug and Fix
- Double-click the violation message. The HDL window highlights the RTL line where the function value is returned.
## Potential issues (range mismatch)
- A violation is reported when there is an order mismatch between the return type and the return value in a function.
## Example code:

function logic [3:0] test_func ();
// no-violation - widths are same, range are in same order
logic [4:1] tmp;
assign test_func = tmp;
endfunction

function logic [11:0] test_func (); 
// no-violation - widths are same
logic [3:0] [2:0] tmp;
return tmp;
endfunction

function logic [2:0] [3:0] test_func (); // no-violation - widths are same
logic [3:0] [2:0] tmp; // rule will not flag for 'swapped ranges'
return tmp;
endfunction

function logic [5:0] test_func ();
logic [2:0] tmp;
logic [4:0] tmp_2;
return tmp + tmp_2; // violation when nocheckoverflow yes
endfunction

function logic [4:0] test_func ();
logic [2:0] tmp;
logic [4:0] tmp_2;
return tmp + tmp_2; // violation when nocheckoverflow no
endfunction

function logic signed [4:0] test_func ();
logic signed [2:0] tmp;
logic [4:0] tmp_2;
return tmp + tmp_2; // violation - signed unsigned
mismatch
endfunction

function logic [2:0] test_func (); // no-violation
return '0;
endfunction

function logic [0:2] test_func ();
logic [2:0] tmp;
return tmp; // violation - order mismatch - ranges are in
reverse order
endfunction

# W126~129
## Rule
- do not use delay values which is non-integer, negative, non-constant or containing X or Z.

out1 = # (8'h1x) in1;
integer i=0;
out2 = #i in;

# W18
## Rule
- Do not infer latches
## Suggested Fix
- Check the inference to make sure it is what you intended. If not, prevent latch inferences by providing an explicit else clause at the end of the if statement, or default clause at the end of the case statement, to prevent inferring the latch.
## Example

process (reset, d)
 begin
 if (reset = '1') then
 q <= d;
 end if;
end process;

# W107
## Rule
- Verilog does not provide a method to check that a connection made to the inputs of a primitive gate (and, or, etc.) is of an appropriate width.If a wider bus is attached, the function simply expands to include the additional bits. This expansion can lead to unexpected behavior if the bus width changes as the design evolves. Thus it is safer to explicitly connect, bit-by-bit, those bits, which should be gated.
## Suggested Fix
- Make connections bit-by-bit. For example, use and (b[0],b[1],b[2].) rather than and(b[0:3]).
# W110
## Rule
- Use this rule to identify the width mismatch between a module port and the net connected to the port of that module instance.
## Suggested Fix
- To debug the violation, double-click the message. The HDL Viewer window highlights the module or the interface instance where a port connection has incompatible width as compared to the port definition.
## Examples

inst IN1 (.in1(a[2:0]+b[2:0]));
// Width of expression, a[2:0]+b[2:0], will be 4 (7+7=14, 4 bits wide)
inst IN2 (.in1(a[2:0]*b[2:0]));
// Width of expression, a[2:0]*b[2:0], will be 6
inst IN3 (.in1(a1[2:0]*b1[2]));
// Width of expression, a[2:0]*b1[2], will be 3
inst IN4 (.in1({1'b0,a[2:0]}));
// Width is 3 bits (leading 0 ignored)
inst IN5 (.in1({1'b1,a[2:0]}));
// Width is 4 bits (1+3 bits)

# W146
## Rule
- Use named-association rather than positional association to connect to an instance
# W156
## Rule
- Do not connect buses in reverse order. Making reversed connections (for example, 15:0 connected to 0:15) is legal but bad design practice and may represent an error.
# W210
## Rule
- Number of connections made to an instance does not match number of ports on master
# W287a
## Rule
- Some inputs to instance are not driven or unconnected
## Suggested Fix
- If you don’t care about the input value, tie it high or low, but do not let it float.
## Examples

module test(in1, in2, clk, out1);
 input in1, in2, clk;
 output out1;
 wire w1, w2;
 assign w1 = in1 & in2;
 and a1(out1, w1, w2);
// Undriven instance input 'w2'
endmodule