# CH14. CMOS Digital Logic Circuits

:::info
**Disclaimer**
If you spot any error, please contact me via my email: [e-mail]
:::

## 14.1 CMOS Logic-Gate Circuits

### 14.1.1 Switch-Level Transistor Model

**NMOS**

**PMOS**

:::info
++Note++. $R_{on}=r_{DS}\simeq\frac{1}{k_nV_{OV}}$ for the MOS transistors.
:::

### 14.1.2 The CMOS Inverter

$Y=\overline{X}$

:::info
++Observation++. Operation of the circuit:
:::

### 14.1.3 General Structure of CMOS Logic


**Pull-up network (PUN)**: consisting of NMOS transistors.
**Pull-down network (PDN)**: consisting of PMOS transistors.

:::info
++Note++. PDN will conduct when $Y=0$ is required (PUN will be off simultaneously). PUN will conduct when $Y=1$ is required (PDN will be off simultaneously).

Examples of PDNs:

Examples of PUNs:
:::

**Alternative circuit symbols**

### 14.1.4 The Two-Input NOR Gate

$Y=\overline{A+B}=\overline{A}\ \overline{B}$

PDN: $Y=0$ when $A=1\lor B=1\Rightarrow\overline{Y}=A+B$
PUN: $Y=1$ when $\overline{A}=1\land\overline{B}=1\Rightarrow Y=\overline{A}\ \overline{B}=\overline{A+B}$

### 14.1.5 The Two-Input NAND Gate

$Y=\overline{AB}=\overline{A}+\overline{B}$

PDN: $Y=0$ when $A=1\land B=1\Rightarrow\overline{Y}=AB$
PUN: $Y=1$ when $\overline{A}=1\lor\overline{B}=1\Rightarrow Y=\overline{A}+\overline{B}=\overline{AB}$

### 14.1.6 A Complex Gate

$Y=\overline{A(B+CD)}=\overline{A}+\overline{B+CD}=\overline{A}+\overline{B}(\overline{C}+\overline{D})$

### 14.1.7 Obtaining the PUN from the PDN and Vice Versa

:::info
++Oberservation++. For the circuits we obtained so far, the PDN and the PUN are dual networks: Where a series branch exists in one, a parallel branch exists in the other.
:::

### 14.1.8 The Exclusive-OR Function

$Y=A\overline{B}+\overline{A}B\Rightarrow \overline{Y}=\overline{A}\ \overline{B}+AB$
($\overline{A}$ and $\overline{B}$ can be obtained using extra inverters $\Rightarrow$ **12** transistors needed in total)

### 14.1.9 Summary of the Synthesis Method

1. PDN can be directly synthesized using the expression of $\overline{Y}$ with uncomplemented variables ($A, B, C...$). If complemented appeared, use extra inverters.
2. PUN can be directly synthesized using the expression of $Y$ with complemented variables ($\overline{A}, \overline{B}, \overline{C}...$). If uncomplemented appeared, use extra inverters.
3. PDN can be obtained from PUN using the duality, and vice versa.

## 14.2 Digital Logic Inverters

### 14.2.1 The Voltage-Transfer Characteristic (VTC)

:::success
++Recall++. VTC of a transistor amplifier
:::

$\Rightarrow$ **The (approximated) VTC of an inverter**

### 14.2.2 Noise Margins


$\Rightarrow NM_L=V_{IL}-V_{OL}$, $NM_H=V_{OH}-V_{IH}$

:::info
++Note++. Important parameters of the VTC of the logic inverter
and their formal definitions.
:::

### 14.2.3 The Ideal VTC

### 14.2.4 Inverter Implementation

**A simple inverter**

$V_{OL}=\frac{R_{on}}{R+R_{on}}V_{DD}$

**An inverter which utilizes a pair of complementary switches**

$V_{OH}=V_{DD}$, $V_{OL}=0$

#### Resistively Loaded MOS Inverter

($V_x=1/k_nR_D$)

$V_{OH}=V_{DD}$, $V_{IH}=V_t+1.63\sqrt{V_{DD}V_x}-V_x$
$V_{OL}\simeq\frac{V_{DD}}{1+[(V_{DD}-V_t)/V_x]}$, $V_{IL}=V_t+V_x$
$V_M=V_t+\sqrt{2(V_{DD}-V_t)V_x+V_x^2}-V_x$

:::info
++Observation++. The required $R_D$ in this circuit design is usually very large. Also, this design causes static power dissipation when the output is low.
:::

#### Pseudo-NMOS Inverter


## 14.3 The CMOS Inverter


### 14.3.1 Circuit Operation

**When $v_I$ is high**
($r_{DSN}=1/\left[k_n'\left(\frac{W}{L}\right)_n(V_{DD}-V_{tn})\right]$)

**When $v_I$ is low**
($r_{DSP}=1/\left[k_p'\left(\frac{W}{L}\right)_p(V_{DD}-|V_{tp}|)\right]$)

:::info
++Observation++.
- The output voltage levels are $0$ and $V_{DD}$.
- No static power dissipation.
- A low-resistance path exists between the output terminal and ground or $V_{DD}$.
- The active pull-up and pull-down devices provide the inverter with high output-driving capability in both directions.
- The input resistance of the inverter is infinite.
:::

### 14.3.2 The Voltage-Transfer Characteristic (VTC)

:::success
++Recall++. For MOSFET in triode region, $i_D=k_n\left(V_{OV}v_{DS}-\frac{1}{2}v_{DS}^2\right)$
:::

$\Rightarrow$
$i_{DN}=k_n'\left(\frac{W}{L}\right)_n\left[(v_I-V_{tn})v_O-\frac{1}{2}v_O^2\right], \text{for }v_O\leq v_I-V_{tn}$
$i_{DN}=k_n'\left(\frac{W}{L}\right)_n(v_I-V_{tn})^2, \text{for }v_O\geq v_I-V_{tn}$
$i_{DP}=k_p'\left(\frac{W}{L}\right)_p\left[(V_{DD}-v_I-|V_{tp}|)(V_{DD}-v_O)-\frac{1}{2}(V_{DD}-v_O)^2\right], \text{for }v_O\geq v_I+|V_{tp}|$
$i_{DP}=k_p'\left(\frac{W}{L}\right)_p(V_{DD}-v_I-|V_{tp}|)^2, \text{for }v_O\leq v_I+|V_{tp}|$

:::info
++Note++. For NMOS and PMOS to be matched, we make
$\frac{W_p}{W_n}=\frac{\mu_n}{\mu_n}$
:::


**Determining $V_{IH}$**: ($Q_P$ in saturation, $Q_N$ in triode reigon)
$\Rightarrow (v_I-V_t)v_O-\frac{1}{2}v_O^2=\frac{1}{2}(V_{DD}-v_I-V_t)^2$
$\Rightarrow v_O+(v_I-V_t)\frac{dv_O}{dv_I}-v_O\frac{dv_O}{dv_I}=-(V_{DD}-v_I-V_t)$
$\frac{v_O}{v_I}=-1\Rightarrow v_O=V_{IH}-\frac{V_{DD}}{2}\Rightarrow V_{IH}=\frac{1}{8}(5V_{DD}-2V_t)$

**Determining $V_{IL}$**: ($Q_N$ in saturation, $Q_P$ in triode reigon)
By symmetry ($V_{IH}-\frac{V_{DD}}{2}=\frac{V_{DD}}{2}-V_{IL}$) $\Rightarrow V_{IL}=\frac{1}{8}(3V_{DD}+2V_t)$

$\Rightarrow NM_H=V_{OH}-V_{IH}=\frac{1}{8}(3V_{DD}+2V_t)$
$\Rightarrow NM_L=V_{IL}-V_{OH}=\frac{1}{8}(3V_{DD}+2V_t)$

### 14.3.3 The Situation When $Q_N$ and $Q_P$ Are Not Matched

$V_M=\frac{r(V_{DD}-|V_{tp}|)+V_{tn}}{r+1}$ ($r=\sqrt{\frac{k_p}{k_n}}=\sqrt{\frac{\mu_p W_p}{\mu_n W_n}}$)

:::info
++Observation++. $V_M$ increase (very slightly) with $r$.
:::

## Summary

- A CMOS logic gate consists of an NMOS PDN (pull-down network) and an PMOS PUN (pull-up network).
- PDN can be directly synthesized using the expression of $\overline{Y}$ with uncomplemented variables ($A, B, C...$). If complemented appeared, use extra inverters.
- PUN can be directly synthesized using the expression of $Y$ with complemented variables ($\overline{A}, \overline{B}, \overline{C}...$). If uncomplemented appeared, use extra inverters.
- PDN can be obtained from PUN using the duality, and vice versa.
- The VTC and important parameters:
- Summary of important static characteristics of the CMOS logic inverter:

## Practice

- 14.1, 14.2, 14.3, 14.4, 14.5
- 14.16, 14.18, 14.22
- 14.30, 14.32