---
# System prepended metadata

title: 109期中-解析(施工中)
tags: [test, computer organization, thu]

---

###### tags: `computer organization` `test` `thu`
{%hackmd theme-dark %}
# 109期中-解析(施工中)
## 1.下列何者非電腦系統匯流排(System Bus) 
#### A. Address Bus   
#### B. Control Bus 
#### C. Data Bus 
#### D. I/O Bus
### Answer:D

## 2. CPU的執行時間與下列何者無關？
#### A. Instruction Count 
#### B. CPI 
#### C. Power 
#### D. Clock Cycle Time
### Answer:C

## 3.電腦的CPU內部結構不包含
#### A. ALU+Countol Unit 
#### B. Memory 
#### C. Register 
#### D. Cache+Cache Controller
### Answer:B

## 4. What is the range of addresses for conditional branches in MIPS(1K=1024)
#### A. Addresses between 0 and 64K-1
#### B. Addresses between 0 and 256K-1
#### C. Addresses up to about 32K before the branch to about 32K after
#### D. Addresses up to about 128K before the branch to about 128K-1 after
### Answer:D

## 5. 下面二個指令合成等於是那一個指令
```assembly
slt $t0, $s1, $s2 
bne $t0, $zero, L 
```
#### A. bge $s1, $s2, L 
#### B. beq $t0, $zero, L 
#### C. beg $s1, $s2, L 
#### D. blt $s1, $s2, L
### Answer:D

## 6. 請說明 Big Endian 與 Little Endian 的差異。請以儲存 12345678H(4Byte)的資料做說明

Big Endian: most-significant byte at least address of a word.
Little Endian: least-significant byte at least address.
#### 位址 0 1 2 3 4 5 6 7
(BIG) : 1 2 3 4 5 6 7 8 
#### 位址 0 1 2 3 4 5 6 7
(LITTLE) : 8 7 6 5 4 3 2 1

## 7. 請說明 jr 與 jal 的用途與差異。

jr指令為使用暫存器的跳躍指令，跳躍位址在暫存器中，用於switch和程序返回

jal指令為帶有連結功能的直接跳躍指令，指令的跳躍地址在指令中，跳躍發生時把返回地址存放到R31暫存器中，用於程序呼叫。

## 8.(題組)
#### a. 請用圖示說明MIPS的定址法(Addressing): Register Addressing、Base Addressing、PC-Relative Addressing 及Pseudo direct Addressing。(搭配MIPS R-I-J指令格式解釋)

- MIPS addressing mode

    ![](https://i.imgur.com/2x13H1B.gif)

#### b. 說明Base Addressing, PC-Relative Addressing的差異。
-  Base Addressing和PC-Relative Addressing的差異在於Base  Addressing 在計算位址時是暫存器加上指令常數。
-  PC-Relative Addressing 在計算位址時則是PC加上指令常數。

#### c. 為何Immediate Addressing最有效率？
- immediate Addressing最有效率的原因是不需要去找位址。

## 9. 何為 Pipeline Hazards (危障)，與前饋(Forwarding)請詳述

Pipeline Hazards：在進行管線化時有些情況會導致下個指令無法正確執行

Forwarding： 不等到第一個指令將結果寫回，直接在第一個指令完成 Execution 時將結果傳送給第二個指令的 Execution Input 。

## 10. Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B and C) in the instruction set. M1 has a clock rate of 80 MHz and M2 has a clock rate of 100 MHz. The average number of cycles for each instruction class and their frequencies (for a typical program) are as follow:

|Instruction Class|Machine M1 - Cycles/Instruction Class | Machine M2 - Cycles/Instruction Class | Frequency |
|:----------------|:---------|:----------|:---------|
|A                |1        |2        |60%            |
|B                | 2        |3            |30%        |
|C                | 4        |4            |10%        |

### (a) Calculate the average CPI for each machine, M1 and M2.

- M1：$$1\cdot0.6+2\cdot0.3+4\cdot0.1=1.6$$
- M2：$$2\cdot0.6+3\cdot0.3+4\cdot0.1=2.5$$

### (b) Calculate the average MIPS ratings for each machine, M1 and M2.

- M1：$$\frac{80\cdot 10^6}{1.6\cdot 10^6}$$
- M2：$$\frac{100\cdot 10^6}{2.5\cdot 10^6}$$

## 11. Please list at least five components for constructing a MIPS processor. 

- ALU
- Register
- Mux
- Data memory
- Sign-extend

## 12. We have a processor with the following components, please draw the data path on those components and list all control flag values (Gray part) for `sw` and `beq` instructions, respectively(個別地).
![](https://i.imgur.com/zF1lP60.png)

### A. `add rd, rs, rt`
- RegDst：1
- RegWrite：1
- ALUSrc：0
- PCsrc：0
- MemRead：0
- MemWrite：0
- MemtoReg：0
- ALUOp：10
- ALU control：0010

### B. `sw rs, offset(rt)`
- RegDst：X
- RegWrite：0
- ALUSrc：0
- PCsrc：1, if Zero=1, otherwise 0
- MemRead：0
- MemWrite：0
- MemtoReg：X
- ALUOp：0110
- ALU control：01
![](https://i.imgur.com/kDaSc7w.png)









