###### tags: `computer organization` `test` `thu`
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# 104期中-解析

## 1. Alternative compiled code sequences using instructions in classes A, B, C and D in the following table. Please identify which code sequence will get smaller average CPI than the other?
| Class | A | B | C | D |
| ----------------- | - | - | - | - |
| CPI for class | 1 | 2 | 3 | 4 |
| IC in sequence 1 | 3 | 3 | 4 | 5 |
| IC in sequence 2 | 4 | 5 | 3 | 4 |
### Solution
- IC in sequence 1：
$$\frac{(3\cdot 1+3\cdot 2+4\cdot 3+5\cdot 4)}{(3+3+4+5)}=2$$
- IC in sequence 2：$$\frac{(4\cdot1+5\cdot2+3\cdot3+4\cdot4)}{(4+5+3+4)}=2.4375$$

## 2. 此為題組
### a. 請用圖示說明MIPS的定址法(Addressing): Register Addressing、Base Addressing、PC-Relative Addressing 及Pseudo direct Addressing。(搭配MIPS R-I-J指令格式解釋)

- MIPS addressing mode

### b. 說明Base Addressing, PC-Relative Addressing的差異。
- Base Addressing和PC-Relative Addressing的差異在於Base Addressing 在計算位址時是暫存器加上指令常數。
- PC-Relative Addressing 在計算位址時則是PC加上指令常數。
- Base Addressing和PC-Relative Addressing的差異在於Base Addressing 在計算位址時是暫存器加上指令常數。PC-Relative Addressing 在計算位址時則是PC加上指令常數。
### c. 為何Immediate Addressing最有效率？
* immediate Addressing最有效率的原因是不需要去找位址。

#### 參[筆記-Chapter 2](/2bLoHpJmS9WU81IlOeBHvQ)

## 3. Please list all components for constructing a MIPS processor.
### Solution
ALU, Registers, Data memory, Mux, Sign-extend, PC, Adder, Instruction Memory
## 4.

### A. `lw rt, Offset(rs)`
- RegDst：0
- RegWrite：1
- ALUSrc：1
- PCSrc：0
- MemRead：1
- MemWrite：0
- MemtoReg：1
- ALUOp：00
- ALU control：0010

### B. `beq r1, r2, label`
- RegDst：X
- RegWrite：0
- ALUSrc：0
- PCSrc：1, if Zero=1
- MemRead：0
- MemWrite：0
- MemtoReg：X
- ALUOp：01
- ALU control：0110

## 5. 何謂Pipeline Hazards (危障)
在進行管線化時下一道指令在下個時脈週期中無法順利正確執行

## 6. Please use the follow example to demonstrate the result after applying the technologies of ***Delay Branch*** and ***Optimization of Delay Branch***, respectively.

### Note
1. X, Y and Z are memory addresses.
2. A, B and C are registers.
3. Pipeline is I-E-D three stages. Compiler will insert noop for pipeline stall.

| Address | Normal Branch |
|:-------:| ------------- |
| 0100 | `Load A, X` |
| 0104 | `Add A, 1` |
| 0108 | `Jump 0114` |
| 010C | `Add A, B` |
| 0110 | `Sub C, B` |
| 0114 | `Store A, Z` |
| 0118 | `Load A, Y` |

### a. Draw the pipeline diagram for delay branch with inserting noop.

### b. Draw the pipeline diagram by using optimization of delay branch.