---
# System prepended metadata

title: 105期中-解析
tags: [test, computer organization, thu]

---

###### tags: `computer organization` `test` `thu`
{%hackmd theme-dark %}
# 105期中-解析
## 1. 請說明`jr`與`jal`的用途與差異。
jr指令為使用暫存器的跳躍指令，跳躍位址在暫存器中，用於switch和程序返回

jal指令為帶有連結功能的直接跳躍指令，指令的跳躍地址在指令中，跳躍發生時把返回地址存放到R31暫存器中，用於程序呼叫。
## 2. Consider two different implementations, M1 and M2, of the same instruction set. There are three classes of instructions (A, B and C) in the instruction set. M1 has a clock rate of 80 MHz and M2 has a clock rate of 100 MHz. The average number of cycles for each instruction class and their frequencies (for a typical program) are as follow:

|Instruction Class|Machine M1 - Cycles/Instruction Class | Machine M2 - Cycles/Instruction Class | Frequency |
|:----------------|:---------|:----------|:---------|
|A                |1        |2        |60%            |
|B                | 2        |3            |30%        |
|C                | 4        |4            |10%        |


### (a) Calculate the average CPI for each machine, M1 and M2.

- M1：$$1\cdot0.6+2\cdot0.3+4\cdot0.1=1.6$$
- M2：$$2\cdot0.6+3\cdot0.3+4\cdot0.1=2.5$$

### (b) Calculate the average MIPS ratings for each machine, M1 and M2.

- M1：$$\frac{80\cdot 10^6}{1.6\cdot 10^6}$$
- M2：$$\frac{100\cdot 10^6}{2.5\cdot 10^6}$$


## 4. Please list all components for constructing a MIPS processor.
### Solution
- ALU
- Registers
- Data memory
- Mux
- Sign-extend

## 5. Please fill the blank each:
![](https://i.imgur.com/FF0zadl.png)
43 9 19 0 (不確定

## 6. We have a processor with the following components, please draw the data path on those components and list all control flag values (Gray part) for `sw` and `beq` instructions, respectively(個別地).
### A. `sw rs, offset(rt)`
- RegDst：X
- RegWrite：0
- ALUSrc：1
- PCsrc：0
- MemRead：0
- MemWrite：1
- MemtoReg：X
- ALUOp：00
- ALU control：0010

### B. `beq r1, r2, Label`
- RegDst：X
- RegWrite：0
- ALUSrc：0
- PCsrc：1, if Zero=1, otherwise 0
- MemRead：0
- MemWrite：0
- MemtoReg：X
- ALUOp：01
- ALU control：0110
![](https://i.imgur.com/kDaSc7w.png)

![](https://i.imgur.com/zF1lP60.png)
## 7. 何謂Pipeline, please describe the five stages (IF-ID-EX-MEM-WB) of a MIPS CPU (one step per stage) as an example.
pipeline是一種讓多個指令可以重疊執行的技術，能增進計算機的效能。
|Stages|作用     |
|:-----|:------ |
|IF    |讀取指令  |
|ID    |解碼指令  |
|EX    |執行     |
|MEM   |記憶體存取|
|WB    |寫回暫存器|


