---
# System prepended metadata

title: BCD to Decimal Decoder with Preset/Reset

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# BCD to Decimal Decoder with Preset/Reset
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**學號:B1095105
姓名:李彥霆
指導老師:林宏益**

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# 1.實驗目的
實現BCD to Decimal Decoder(RTL、testbench)並驗證其正確性
> ![](https://hackmd.io/_uploads/BkLIgHfWa.png)
> 實驗所附真值表

# 2.實驗結果
###  RTL
```
module decoder4_to_10( in,out, reset_n, preset);
input [3:0]  in;
input  reset_n;
input preset;
output [9:0] out;
reg [9:0] out;

always @( in or  reset_n or preset)
begin
    if ( reset_n)
    begin
        if (~preset)
        begin
            out=8'd0;
            case (in)
                4'b0000:
                    out=~10'b0000000001;
                4'b0001:
                    out=~10'b0000000010;
                4'b0010:
                    out=~10'b0000000100;
                4'b0011:
                    out=~10'b0000001000;
                4'b0100:
                    out=~10'b0000010000;
                4'b0101:
                    out=~10'b0000100000;
                4'b0110:
                    out=~10'b0001000000;
                4'b0111:
                    out=~10'b0010000000;
                4'b1000:
                    out=~10'b0100000000;
                4'b1001:
                    out=~10'b1000000000;
                default:
                    out=10'b1111111111;
            endcase
        end
        else
            out = 10'b0000001111;
    end
    else
        out=0;
end
endmodule
```
### Testbench
```
module decoder_tb;
wire [9:0] out;
reg reset_n;
reg preset;
reg [3:0] in;
integer i;
integer j;

initial
begin
    $dumpfile("decoder4_to_10.vcd" );
    $dumpvars(0, s);

    $monitor( " reset_n=%b,preset=%b in(DCBA)=%b, out=%b ",  reset_n,preset, in, out);
    for ( i=0; i<16; i=i+1)
    begin
        reset_n = 1;
        preset = 0;
        {in}  = i;
        #50;
    end
    for ( i=0; i<16; i=i+1)
    begin
        reset_n = 0;
        preset = 1;
        {in}  = i;
        #50;
    end
    for ( i=0; i<16; i=i+1)
    begin
        reset_n = 1;
        preset = 1;
        {in}  = i;
        #50;
    end
    #50 $finish;
end
decoder4_to_10 s(in,out, reset_n, preset);

endmodule
```
預先設定好input 0000~1111所對應之值，接著由reset_n、preset決定output

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###  Vivado波形圖
> ![](https://hackmd.io/_uploads/BkrGYPMZ6.png)
> reset_n = 1, preset = 0

> ![](https://hackmd.io/_uploads/Hy3E5DGZ6.png)
> reset_n = 0, preset = X

> ![](https://hackmd.io/_uploads/HJDjqvfZa.png)
> reset_n = 1, preset = 1


### Vivado schematic圖
![](https://hackmd.io/_uploads/Skb6zs-bT.png)
Synthesis前


![](https://hackmd.io/_uploads/S1_gHoWba.png)
Synthesis後

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### I/O planning
![](https://hackmd.io/_uploads/Hk7otOGbp.png)

---
### Floor planning
![](https://hackmd.io/_uploads/Hkre5ufWT.png)

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### On-Chip Power
![](https://hackmd.io/_uploads/ryeocdfZp.png)

---

### PYNQ-Z2

>![image.png](https://hackmd.io/_uploads/SJCIwNMQ6.png)
>
>![image.png](https://hackmd.io/_uploads/H110v4G7a.png)
>reset_n = 0,preset=0,1

>![image.png](https://hackmd.io/_uploads/ByBLdNG7p.png)
>reset_n=1,preset=1,out=1111000000

>![image.png](https://hackmd.io/_uploads/ByX3OVz7a.png)
>reset_n=1,preset=0,in=0,out=0111111111

>![image.png](https://hackmd.io/_uploads/ByXet4GXp.png)
>reset_n=1,preset=0,in=1,out=1011111111

>![image.png](https://hackmd.io/_uploads/H1lEMYEfma.png)
>reset_n=1,preset=0,in=2,out=1101111111

>![image.png](https://hackmd.io/_uploads/SyNvF4GQp.png)
>reset_n=1,preset=0,in=3,out=1110111111

>![image.png](https://hackmd.io/_uploads/B1CS94fQT.png)
>reset_n=1,preset=0,in=4,out=1111011111

>![image.png](https://hackmd.io/_uploads/ry6t94GXT.png)
>reset_n=1,preset=0,in=5,out=1111101111

>![image.png](https://hackmd.io/_uploads/Skqh9VzX6.png)
>reset_n=1,preset=0,in=6,out=1111110111

>![image.png](https://hackmd.io/_uploads/SJZgj4GQp.png)
>reset_n=1,preset=0,in=7,out=111111011

>![image.png](https://hackmd.io/_uploads/H1-IiEfmp.png)
>reset_n=1,preset=0,in=8,out=111111101

>![image.png](https://hackmd.io/_uploads/BysvoVM76.png)
>reset_n=1,preset=0,in=9,out=111111110

>![image.png](https://hackmd.io/_uploads/HyELe6DQ6.png)
>reset_n=1,preset=0,in=10~15,out=111111111



# 3.實驗討論
 我寫的RTL是用case的方式去選擇輸出結果，跟生成出來的電路圖滿相近的，會有一個記憶體先儲存相對應的input/output，再由reset_n、preset決定輸出是否需要重整或預設；若是用算術邏輯的方式撰寫所生成出的電路圖則會跟題目所附的參考資料中的電路圖十分相似。
 功率分析報告則可以發現占比最高的是在I/O部分，可能是因為我用case撰寫，若是將真值表的每一項輸出(out[0 ~ 9])改用算術邏輯(&、|、~)的方式撰寫，Logic的power可能就會提高不少。
 
#  4.實驗心得
這次的實驗我是從真值表下手，可以用case或是大量算術邏輯的方式撰寫，而我想到上學期在計算機組織的3 to 8 decoder作業，覺得可以試著從中改寫，在改寫I/O並因應多出的限制reset_n、preset而添加了一些if-else迴圈用以面對不同的輸出，模擬結果也如題目所附真值表相同~!
# 5.參考文獻
https://www.ti.com/lit/ds/sdls109/sdls109.pdf