---
# System prepended metadata

title: 微處理機
tags: [111-1學校上課]

---

###### tags: `111-1學校上課`
# 微處理機
## LAB 1
### 分工表:
* 不知道要打啥
* 不知道要打啥
### 實驗1:七段顯示器解碼電路
#### Main code
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity main is port(
    Z:in std_logic;
    Y:in std_logic;
    X:in std_logic;
    W:in std_logic;
    a:out std_logic;
    b:out std_logic;
    c:out std_logic;
    d:out std_logic;
    e:out std_logic;
    f:out std_logic;
    g:out std_logic
);

end main;
architecture Main of main is 
begin
    process(W ,X ,Y,Z) 
    begin
        a <= ((not W) and (not X) and(not Y) and( Z))or(( W) and (not X) and( Y) and( Z))or(( X) and(not Y) and(not Z))or((W) and (X) and(not Y) );
        b <= ((not W) and ( X) and(not Y) and( Z))or( ( X) and( Y) and( not Z))or(( W) and(X) and(not Z))or((W) and (Y) and( Z) );
        c <= ((not W) and (not X) and(Y) and(not Z))or( ( W) and( X) and( not Z))or(( W) and(X) and( Y)) ;
        d <= ((not X) and (not Y) and(Z) )or( (not W) and( X) and( not Y)and( not Z))or(( X) and(Y) and(Z))or((W) and (not X)and (Y) and(not Z) );
        e <= ((not W) and( Z))or( (not W) and( X) and( not Y))or((not X) and(not Y) and(Z));
        f <= ((not W) and (not X) and(Z) )or( (not W) and( not X) and( Y))or((not W) and(Y) and(Z))or((W) and (X) and(not Y) );
        g <= ((not W) and (not X) and(not Y) )or( (not W) and( X) and( Y) and Z) ;
    end process;
end Main; 
```
#### Pin Setting
![](https://i.imgur.com/OG11xW7.png)
### 實驗2:3個七段顯示器解碼電路
#### main code
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity main is port(
	Z1:in std_logic;
	Y1:in std_logic;
	X1:in std_logic;
	W1:in std_logic;
	a1:out std_logic;
	b1:out std_logic;
	c1:out std_logic;
	d1:out std_logic;
	e1:out std_logic;
	f1:out std_logic;
	g1:out std_logic;
	
	Z2:in std_logic;
	Y2:in std_logic;
	X2:in std_logic;
	W2:in std_logic;
	a2:out std_logic;
	b2:out std_logic;
	c2:out std_logic;
	d2:out std_logic;
	e2:out std_logic;
	f2:out std_logic;
	g2:out std_logic;
	
	Z3:in std_logic;
	Y3:in std_logic;
	X3:in std_logic;
	W3:in std_logic;
	a3:out std_logic;
	b3:out std_logic;
	c3:out std_logic;
	d3:out std_logic;
	e3:out std_logic;
	f3:out std_logic;
	g3:out std_logic
);

end main;
architecture Main of main is 
begin
	process(W1 ,X1 ,Y1,Z1,W2 ,X2 ,Y2,Z2,W3 ,X3 ,Y3,Z3) 
	begin
		a1 <= ((not W1) and (not X1) and(not Y1) and( Z1))or(( W1) and (not X1) and( Y1) and( Z1))or(( X1) and(not Y1) and(not Z1))or((W1) and (X1) and(not Y1) );
		b1 <= ((not W1) and ( X1) and(not Y1) and( Z1))or( ( X1) and( Y1) and( not Z1))or(( W1) and(X1) and(not Z1))or((W1) and (Y1) and( Z1) );
		c1 <= ((not W1) and (not X1) and(Y1) and(not Z1))or( ( W1) and( X1) and( not Z1))or(( W1) and(X1) and( Y1)) ;
		d1 <= ((not X1) and (not Y1) and(Z1) )or( (not W1) and( X1) and( not Y1)and( not Z1))or(( X1) and(Y1) and(Z1))or((W1) and (not X1)and (Y1) and(not Z1) );
		e1 <= ((not W1) and( Z1))or( (not W1) and( X1) and( not Y1))or((not X1) and(not Y1) and(Z1));
		f1 <= ((not W1) and (not X1) and(Z1) )or( (not W1) and( not X1) and( Y1))or((not W1) and(Y1) and(Z1))or((W1) and (X1) and(not Y1) );
		g1 <= ((not W1) and (not X1) and(not Y1) )or( (not W1) and( X1) and( Y1) and Z1) ;
		
		a2 <= ((not W2) and (not X2) and(not Y2) and( Z2))or(( W2) and (not X2) and( Y2) and( Z2))or(( X2) and(not Y2) and(not Z2))or((W2) and (X2) and(not Y2) );
		b2 <= ((not W2) and ( X2) and(not Y2) and( Z2))or( ( X2) and( Y2) and( not Z2))or(( W2) and(X2) and(not Z2))or((W2) and (Y2) and( Z2) );
		c2 <= ((not W2) and (not X2) and(Y2) and(not Z2))or( ( W2) and( X2) and( not Z2))or(( W2) and(X2) and( Y2)) ;
		d2 <= ((not X2) and (not Y2) and(Z2) )or( (not W2) and( X2) and( not Y2)and( not Z2))or(( X2) and(Y2) and(Z2))or((W2) and (not X2)and (Y2) and(not Z2) );
		e2 <= ((not W2) and( Z2))or( (not W2) and( X2) and( not Y2))or((not X2) and(not Y2) and(Z2));
		f2 <= ((not W2) and (not X2) and(Z2) )or( (not W2) and( not X2) and( Y2))or((not W2) and(Y2) and(Z2))or((W2) and (X2) and(not Y2) );
		g2 <= ((not W2) and (not X2) and(not Y2) )or( (not W2) and( X2) and( Y2) and Z2) ;
		
		a3 <= ((not W3) and (not X3) and(not Y3) and( Z3))or(( W3) and (not X3) and( Y3) and( Z3))or(( X3) and(not Y3) and(not Z3))or((W3) and (X3) and(not Y3) );
		b3 <= ((not W3) and ( X3) and(not Y3) and( Z3))or( ( X3) and( Y3) and( not Z3))or(( W3) and(X3) and(not Z3))or((W3) and (Y3) and( Z3) );
		c3 <= ((not W3) and (not X3) and(Y3) and(not Z3))or( ( W3) and( X3) and( not Z3))or(( W3) and(X3) and( Y3)) ;
		d3 <= ((not X3) and (not Y3) and(Z3) )or( (not W3) and( X3) and( not Y3)and( not Z3))or(( X3) and(Y3) and(Z3))or((W3) and (not X3)and (Y3) and(not Z3) );
		e3 <= ((not W3) and( Z3))or( (not W3) and( X3) and( not Y3))or((not X3) and(not Y3) and(Z3));
		f3 <= ((not W3) and (not X3) and(Z3) )or( (not W3) and( not X3) and( Y3))or((not W3) and(Y3) and(Z3))or((W3) and (X3) and(not Y3) );
		g3 <= ((not W3) and (not X3) and(not Y3) )or( (not W3) and( X3) and( Y3) and Z3) ;
	end process;
end Main; 
```
#### pin setting
![](https://i.imgur.com/YIgLKxU.png)
![](https://i.imgur.com/pHXrtMU.png)
#### Modelsim
![](https://i.imgur.com/4fLL0Ra.png)
![](https://i.imgur.com/0kEkPXD.png)
## Lab2
### 分工表:
* 不知道要打啥
* 不知道要打啥
### 實驗1:多位元加法器
#### main code
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.adder_package.all;

Entity main is port(
	a,b:in std_logic_vector(7 downto 0);
	seg1,seg2:out std_logic_vector(0 to 6);
	overflow:out std_logic
);
end main;
architecture Main of main is 
signal cin:std_logic;
signal wire:std_logic_vector(7 downto 0);
signal cout:std_logic_vector(7 downto 0);
singal 
begin
	cin<='0';
	add1 :adder port map(a(0),b(0),cin,wire(0),cout(0));
	add2 :adder port map(a(1),b(1),wire(0),wire(1),cout(1));
	
	add3 :adder port map(a(2),b(2),wire(1),wire(2),cout(2));
	add4 :adder port map(a(3),b(3),wire(2),wire(3),cout(3));
	add5 :adder port map(a(4),b(4),wire(3),wire(4),cout(4));
	add6 :adder port map(a(5),b(5),wire(4),wire(5),cout(5));
	add7 :adder port map(a(6),b(6),wire(5),wire(6),cout(6));
	add8 :adder port map(a(7),b(7),wire(6),overflow,cout(7));
	
	test1 :decoder port map(cout(3 downto 0),seg1);
	test2 :decoder port map(cout(7 downto 4),seg2);
end Main; 
```
#### interface
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package  adder_package is 
	component adder
		port(
			a:in std_logic;
			b: in std_logic;
			cin:in std_logic;
			cout:out std_logic;
			s:out std_logic
		);
	end component adder;
	component decoder
		port(
			sw: in std_logic_vector(3 downto 0);
			seg:out std_logic_vector(0 to 6)
		);
	end component decoder;
end package adder_package;
```
#### ciruit code
##### fulladder
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity adder is port(
	a:in std_logic;
	b: in std_logic;
	cin:in std_logic;
	cout:out std_logic;
	s:out std_logic
	);
end adder;

architecture Adders of adder is begin 
	s <= a xor b xor cin;
	cout<=(a and b) or (a and cin) or (b and cin);
end Adders;


```
##### 4 decoder seg
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity decoder is port(
sw: in std_logic_vector(3 downto 0);
seg:out std_logic_vector(0 to 6)
);

end decoder;
architecture Decoder of decoder is 
begin
    process(sw) 
        variable c:integer:=to_integer(unsigned(sw));
    begin
            case (c) is
                when  0 => seg <= "0000001"; -- 0
                when  1 => seg <= "1001111"; -- 1
                when  2 => seg <= "0010010"; -- 2
                when  3 => seg <= "0000110"; -- 3
                when  4 => seg <= "1001100"; -- 4
                when  5 => seg <= "0100100"; -- 5
                when  6 => seg <= "0100000"; -- 6
                when  7 => seg <= "0001111"; -- 7
                when  8 => seg <= "0000000"; -- 8
                when  9 => seg <= "0001100"; -- 9
                when 10 => seg <= "0001000"; -- 10
                when 11 => seg <= "1100000"; -- 11
                when 12 => seg <= "1110010"; -- 12
                when 13 => seg <= "1000010"; -- 13
                when 14 => seg <= "0110000"; -- 14
                when 15 => seg <= "0111000"; -- 15
                when others => seg <= "1111111"; -- error
            end case;
    end process;
end Decoder; 
```
#### PinMode
![](https://i.imgur.com/LgDz1zD.png)
![](https://i.imgur.com/ukJ1yO9.png)
### 實驗2:多位元減法器
#### main code
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.adder_package.all;

Entity main is port(
	a,b:in std_logic_vector(7 downto 0);
	seg1,seg2:out std_logic_vector(0 to 6);
	overflow:out std_logic
);
end main;
architecture Main of main is 
signal cin:std_logic;
signal wire:std_logic_vector(8 downto 0);
signal cout:std_logic_vector(7 downto 0);
signal inv_b:std_logic_vector(7 downto 0);
begin
	cin<='1';
	inv_b <= not b;
	add1 :adder port map(a(0),inv_b(0),cin,wire(0),cout(0));
	add2 :adder port map(a(1),inv_b(1),wire(0),wire(1),cout(1));
	add3 :adder port map(a(2),inv_b(2),wire(1),wire(2),cout(2));
	add4 :adder port map(a(3),inv_b(3),wire(2),wire(3),cout(3));
	add5 :adder port map(a(4),inv_b(4),wire(3),wire(4),cout(4));
	add6 :adder port map(a(5),inv_b(5),wire(4),wire(5),cout(5));
	add7 :adder port map(a(6),inv_b(6),wire(5),wire(6),cout(6));
	add8 :adder port map(a(7),inv_b(7),wire(6),wire(8),cout(7));
	overflow <= wire(8) xor wire(7);
	test1 :decoder port map(cout(3 downto 0),seg1);
	test2 :decoder port map(cout(7 downto 4),seg2);
end Main; 
```

#### interface
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package  adder_package is 
	component adder
		port(
			a:in std_logic;
			b: in std_logic;
			cin:in std_logic;
			cout:out std_logic;
			s:out std_logic
		);
	end component adder;
	component decoder
		port(
			sw: in std_logic_vector(3 downto 0);
			seg:out std_logic_vector(0 to 6)
		);
	end component decoder;
end package adder_package;
```
#### ciruit code
##### fulladder
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity adder is port(
	a:in std_logic;
	b: in std_logic;
	cin:in std_logic;
	cout:out std_logic;
	s:out std_logic
	);
end adder;

architecture Adders of adder is begin 
	s <= a xor b xor cin;
	cout<=(a and b) or (a and cin) or (b and cin);
end Adders;


```
##### 4 decoder seg
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity decoder is port(
sw: in std_logic_vector(3 downto 0);
seg:out std_logic_vector(0 to 6)
);

end decoder;
architecture Decoder of decoder is 
begin
    process(sw) 
        variable c:integer:=to_integer(unsigned(sw));
    begin
            case (c) is
                when  0 => seg <= "0000001"; -- 0
                when  1 => seg <= "1001111"; -- 1
                when  2 => seg <= "0010010"; -- 2
                when  3 => seg <= "0000110"; -- 3
                when  4 => seg <= "1001100"; -- 4
                when  5 => seg <= "0100100"; -- 5
                when  6 => seg <= "0100000"; -- 6
                when  7 => seg <= "0001111"; -- 7
                when  8 => seg <= "0000000"; -- 8
                when  9 => seg <= "0001100"; -- 9
                when 10 => seg <= "0001000"; -- 10
                when 11 => seg <= "1100000"; -- 11
                when 12 => seg <= "1110010"; -- 12
                when 13 => seg <= "1000010"; -- 13
                when 14 => seg <= "0110000"; -- 14
                when 15 => seg <= "0111000"; -- 15
                when others => seg <= "1111111"; -- error
            end case;
    end process;
end Decoder; 
```

#### Pinmode
![](https://i.imgur.com/LgDz1zD.png)
![](https://i.imgur.com/ukJ1yO9.png)