###### tags: `110-2學校上課`
# 數位期末考筆記
## IC(EP4CE115F29C7)
http://www.terasic.com.tw/attachment/archive/502/DE2_115_User_manual.pdf
## library
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
```
## ENTITY
```vhdl=
ENTITY logic is port(
A:in Std_logic;
B:in std_logic_vector(9 downto 0);
c:in std_logic_vector(9 downto 0);
D:out std_logic_vector(10 downto 0)
);
end logic;
```
## INT_ARRAY
```vhdl=
TYPE int_array is array(integer range<>) of integer;
CONSTANT C1:int_array(0 to 9):=(1,2,3,4,5,6,7,8,9,10);
```
## architecture
```vhdl=
architecture Logic of logic is begin
end Logic;
```
## variable
```vhdl=
variable X:integer:=0;
variable y:std_logic:='0';
```
## if
```vhdl=
if X>1 then
X:= to_integer(unsigned(B)+unsigned(C));
D<= std_logic_vector(to_unsigned(X,11));
elsif X<1 then
X:= to_integer(unsigned(B)+unsigned(C));
D<= std_logic_vector(to_unsigned(X,11));
else
X:= to_integer(unsigned(B)+unsigned(C));
D<= std_logic_vector(to_unsigned(X,11));
end if;
```
## switch/case
```vhdl=
case(x) is
when 1 =>
X:= to_integer(unsigned(B)+unsigned(C));
D<= std_logic_vector(to_unsigned(X,11));
when others=>
X:= to_integer(unsigned(B)+unsigned(C));
D<= std_logic_vector(to_unsigned(X,11));
end case;
```
## logic_vector to integer
```vhdl=
to_integer(unsigned(B)+unsigned(C))
```
## integer to logic_vector
```vhdl=
std_logic_vector(to_unsigned(X,11));
```
## 7493
## 7490
## 7492
## 基本邏輯
## 正反器
## 74138
## 期末考
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity logic is port(
clk:in std_logic;
sw: in std_logic;
seg:out std_logic_vector(6 downto 0)
);
constant M:integer:=35000000;
end logic;
architecture Counter of logic is
begin
process(clk,sw)
variable c:integer:=0;
variable N:integer:=2;
begin
if sw='1' AND rising_edge(clk) then
c:= (c+1) mod M;
if c=M-1 then
N:=(N+1)mod 5;
case (N+2) is
when 0 => seg <= "1000000"; -- 0
when 1 => seg <= "1111001"; -- 1
when 2 => seg <= "0100100"; -- 2
when 3 => seg <= "0110000"; -- 3
when 4 => seg <= "0011001"; -- 4
when 5 => seg <= "0010010"; -- 5
when 6 => seg <= "0000010"; -- 6
when 7 => seg <= "1111000"; -- 7
when 8 => seg <= "0000000"; -- 8
when 9 => seg <= "0010000"; -- 9
when others => seg <= "1111111"; -- error
end case;
end if;
end if;
end process;
end Counter;
```
Sign in with Wallet
Connect another wallet