---
# System prepended metadata

title: 期中考sheet
tags: [111-1學校上課]

---

###### tags: `111-1學校上課`
# 期中考sheet
## IC(EP4CE115F29C7)
http://www.terasic.com.tw/attachment/archive/502/DE2_115_User_manual.pdf
## generic 常數
```vhdl=
--請打在entity is 跟 
generic (N:integer := 8);
```
## library 
```vhdl=
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
```
## ENTITY
```vhdl=
ENTITY logic is port(
    腳位設定
);
end logic;
```
## singnal
當你需要在電路多於線路，請在architecture中is 跟 begin之間進行宣告
## INT_ARRAY
```vhdl=
    TYPE int_array is array(integer range<>) of integer;
    CONSTANT C1:int_array(0 to 9):=(1,2,3,4,5,6,7,8,9,10);
```
## architecture 
```vhdl=
    architecture Logic of logic is begin
        
    end Logic;
```
## variable
```vhdl=
variable X:integer:=0;
variable y:std_logic:='0';
```
## logic_vector to integer
```vhdl=
    to_integer(unsigned(B)+unsigned(C))
```
## integer to logic_vector
```vhdl=
    std_logic_vector(to_unsigned(X,11));
```
## component+package
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package  打包名稱 is 
	component 名稱
		port(
			腳位
		);
	end component 打包名稱;
	
end package BCD_package;
```
**請名稱檔名要一致，否則會抓不到**
**若要在main引用請use work.打包名稱.all;**
## If
```vhdl=
--一定要在porcess使用
if 條件 then
    code1;
elsif 
    code2;
.
.
else
    code3;
end if;    
```
## case
```vhdl=
--一定要在porcess使用
case (sw) is
    when 條件=>code1;
    when 條件=>code2;
    when 條件=>code3;
    when others =>code4;
end case;    
```
## for
```vhdl=
for i in 0 to 10 generate 
    code1
end  generate 
for i in 10 downto 0 generate 
    code1
end  generate     
```
## 物件使用
```vhdl=
--腳位輸入順序照定義，也可以指定
隨編一個名稱:你設定的component名稱 port map(腳位1);
隨編一個名稱:你設定的component名稱 port map(名稱1=>腳位1,名稱2=>腳位2);
```
## 7 seg decoder
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity logic is port(
sw: in std_logic_vector(3 donto 0);
seg:out std_logic_vector(6 downto 0)
);
end logic;
architecture Counter of logic is 
	
begin
	process(sw) 
		case (sw) is
			when 0 => seg <= "1000000"; -- 
			when 1 => seg <= "1111001"; -- 
			when 2 => seg <= "0100100"; -- 
			when 3 => seg <= "0110000"; -- 
		    when 4 => seg <= "0011001"; -- 
			when 5 => seg <= "0010010"; -- 
			when 6 => seg <= "0010010"; -- 
			when 7 => seg <= "1111000"; -- 
			when 8 => seg <= "0000000"; -- 
			when 9 => seg <= "0010000"; -- 
			when others => seg <= "1111111"; -- error
		end case;
	end process;

end Counter; 
```
## 使用物件ex
```vhdl=
Gen_dff : for i in 0 to N-1 generate 
		dff:dff1 port map(D(i),clk,not clear,pr(i),qo(i));
	end  generate ;
```
