---
# System prepended metadata

title: LAB8

---

# LAB8
## 環形振盪器
```vhdl
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


Entity main is 
generic(n:integer := 31);
port(
    enable : in std_logic;
    ck_out : out std_logic
);
end main;
architecture Main of main is 
signal wire:std_logic_vector(0 to n-1);
begin 
    ck_out<=wire(n-1);
    wire(0)<=(not wire(n-1)) and enable;
    inv:for i in 1 to n-1 generate
        wire(i) <= not wire(i-1);
    end generate;
end Main;
```
## 8對1多工器
```vhdl=
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux8to1 is port(
    w0, w1, w2, w3, w4, w5, w6, w7 : in std_logic;
	 s : in std_logic_vector(2 downto 0);
	 f : out std_logic
);
end mux8to1;
architecture Mux8to1 of mux8to1 is 
begin
	process(s) begin
		case s(2 downto 0) is 
			when "000" => f <=  w0 ;
			when "001" => f <=  w1 ;
			when "010" => f <=  w2 ;
			when "011" => f <=  w3 ;
			when "100" => f <=  w4 ;
			when "101" => f <=  w5 ;
			when "110" => f <=  w6 ;
			when "111" => f <=  w7 ;
		end case;
	end process;
end Mux8to1; 
```
## 除頻電路50M
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity divider_n is
    generic(divisor:integer:=50000000);         -- 因為要產生1Hz的Cclock, 所以定義除數為4000000
port(
    clk_50M: in std_logic;
    clk_out: out std_logic
);
end divider_n;

architecture Divider_n of divider_n is
    signal cnt2 : std_logic;
begin
    process(clk_50M)
        variable cnt1 : integer range 0 to divisor:=1;
        variable divisor2 : integer range 0 to divisor;
    begin
        divisor2:=divisor/2;
        if(clk_50M'event and clk_50M='1') then         -- cnt1為計數器，累加至4000000時歸0
            if cnt1 = divisor then 
                cnt1 := 1;
            else
            cnt1 := cnt1 + 1;
            end if;
        end if;

        if(clk_50M'event and clk_50M='1') then
            if((cnt1 = divisor2) or (cnt1 = divisor)) then  --  cn1 為2000000或4000000時，輸出做反向
                cnt2<= not cnt2;
            end if;
        end if;
        clk_out <= cnt2;
    end process;
end Divider_n;

```
## 比較器
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comparator is
generic (width : integer := 64);
port(
    val_a : in std_logic_vector(width-1 downto 0);
	 val_b : in std_logic_vector(width-1 downto 0);
	 result : out std_logic
);
end comparator;
architecture Comparator of comparator is 
begin
	process(val_a,val_b)
	variable n:integer range 0 to width-1:=63;
	begin
		if val_a(n)=val_b(n) then
			n := n-1;
		elsif val_a(n) > val_b(n) then
			result <= '1';
		elsif val_a(n) < val_b(n) then
			result <= '0';
		end if;
	end process;
end Comparator; 
```

