2025-12-02 - HackMD

# 2025-12-02 ## [Zhian66](https://hackmd.io/@zhian66/ca25-homework3) How do we evaluate and verify the efficiency improvements when upgrading a 5-stage pipelined CPU from using **bubbles** to implementing **bypassing** from ALU to Register file? ::: success We can evaluate the performance by examining the **CPU cycle counts** and the **waveform**! ::: ### Cycle Count Key Concept: The bypassing version should have a lower cycle count because it eliminates the wasted cycles caused by bubbles (NOPs). 1. Get the initial cycle counts by `CSRRS rd, 0xC00, x0` 2. Execute the data hazards insturction under the bubbles and bypassing mechanisms 3. Get the final cycle counts by `CSRRS` 4. Compute the total cycle counts ### Waveform - Bubbles ver.: Look for "Bubbles" (NOP instructions) or PC holding its value between dependent instructions. - Bypassing ver.: Look for continuous execution (no gaps). Verify that the data is correctly bypassed from the EX or MEM stage directly to the next instruction's input. 1. Generate `.vcd` files using **Verilator** (e.g., `make verilator`, then run with `-vcd dump.vcd`). 2. Inspect signals by opening the `.vcd` file using **Surfer**. 3. Compare the `id_*` and `ex_*` signals between the two versions to confirm the removal of stall cycles.  --- ## [Winstonllllai](https://hackmd.io/@Winstonllllai/ca25-homework3) ### The purpose of functionality of CSR As we dig into ```init.S```, we can see the way to manipulate CSR: ``` # ============================================================================== # CSR (Control and Status Register) Operations # ============================================================================== # Best Practices: # - csrs/csrsi: Set specific bits (read-modify-write, preserves other bits) # - csrc/csrci: Clear specific bits (read-modify-write, preserves other bits) # - csrw/csrrw: Full register write (use only when controlling entire register) # - Avoid magic numbers - use explicit bit shifts for clarity # - Preserve reserved bits per RISC-V Privileged Spec (WARL contract) # ============================================================================== ``` ### Relationship Between CSR and Trap ### How can we utilize it? --- ## [jningmin](https://github.com/jningmin) Csr + 40 single cycle check out riscv spec --- ## [Alex](https://hackmd.io/@K0u7M9pjQwW-yF5gwSpQlA/SkUXP3Ib-l) ### VGA initialization and frame updating procedure