Assignment3: RISC-V CPU

--- tags: computer-arch --- # Assignment3: Your Own RISC-V CPU > Due: ==Dec 10, 2025== :::danger :warning: This assignment is quite challenging, and it is recommended that you dedicate a minimum of **4 full days** to complete it. Otherwise, it may be difficult to produce a meaningful outcome. ::: ## Requirements 1. Following the instructions in [Lab3: Construct a RISC-V CPU with Chisel](https://hackmd.io/@sysprog/B1Qxu2UkZx), engage with the [Chisel Bootcmap](https://github.com/sysprog21/chisel-bootcamp) by completing the provided exercises. * Make sure you have already completed the exercises from Part 1 to Part 3.6 and are familiar with Chisel/Scala. * **Avoid frequent Google searches**, as the provided materials on the lab page are curated to facilitate your learning experience. Simply focus on learning by actively engaging with the prepared materials. * You may encounter various challenges during this process. Please review the [GitHub issues](https://github.com/sysprog21/chisel-bootcamp/issues) and make note of your observations. * Describe the operation of 'Hello World in Chisel' and enhance it by incorporating logic circuit. 2. Adhering to the guidance provided in [Lab3: Construct a RISC-V CPU with Chisel](https://hackmd.io/@sysprog/B1Qxu2UkZx), incorporate the code within the `CA25: Exercise` section in all Scala to pass the corresponding unit tests. This hands-on approach encourages you to learn by actively participating in the process, enhancing your understanding of the subject matter. * **Refrain from copying and pasting your solution directly into the HackMD note**. Instead, provide a concise summary of the various test cases, outlining the aspects of the CPU they evaluate, the techniques employed for loading test program instructions, and the outcomes of these test cases. * For each project (that is, `1-single-cycle`, `2-mmio-trap`, and `3-pipeline`), make sure to carefully read the corresponding `README.md` file and ensure that both make test and make compliance pass completely. Throughout the process, document in detail the issues you encounter and how you overcome them. Note: besides the code regions marked as `TODO`, you may also need to modify other parts of the code. * For `2-mmio-trap`, you must ensure that the Nyancat animation is correctly rendered on the VGA display during Verilator-based simulation, and propose effective approaches to further compress the Nyancat program. * For "CA25: Exercise 21" in `3-pipeline`, you must perform Hazard Detection Summary and Analysis with Chisel and waveforms: - Why do we need to stall for load-use hazards? (Hint: Consider data dependency and forwarding limitations) - What is the difference between "stall" and "flush" operations? (Hint: Compare their effects on pipeline registers and PC) - Why does jump instruction with register dependency need stall? (Hint: When is jump target address available?) - In this design, why is branch penalty only 1 cycle instead of 2? (Hint: Compare ID-stage vs EX-stage branch resolution) - What would happen if we removed the hazard detection logic entirely? (Hint: Consider data hazards and control flow correctness) * For signals involved in filling in the blanks, use the testing framework to output waveform diagrams and describe the changes in key signals of corresponding components when executing different instructions. * Fork the GitHub repository [ca2025-mycpu](https://github.com/sysprog21/ca2025-mycpu) and make commits that correspond to your ongoing efforts accordingly. The progress should always be publicly visible and transparent. $\to$ Read the GitHub documentation, such as [Fork a repo](https://docs.github.com/en/get-started/quickstart/fork-a-repo). 3. Modify the handwritten RISC-V assembly code in [Homework2](https://hackmd.io/@sysprog/2025-arch-homework2) to ensure it functions correctly on the pipelined RISC-V CPU (i.e., `3-pipeline`). Keep the modified code in the `csrc` directory. * Extend the Scala code in `src/test/scala/riscv/singlecycle/CPUTest.scala` to include additional test items related to your modified RISC-V assembly program. Ensure you compile it into an ELF file, which will later be converted into a binary file using the objcopy utility. Refer to the `FibonacciTest` as an example to see how to extend the [ChiselScalatestTester](https://index.scala-lang.org/ucb-bar/chiseltest) for testing the `src/main/resources/fibonacci.asmbin` program. * Execute your program using Verilator and analyze the signals by examining the waveform diagrams. Describe the variations in key signals of the respective components when different instructions are executed. * Ensure that your programs are fully optimized for the pipelined RISC-V processors, eliminating unnecessary stalls while maintaining complete functionality. 5. Write down your thoughts and progress in [HackMD notes](https://hackmd.io/s/features). - Of course, you MUST write in English. - **Avoid using screenshots that solely contain plain text**. Here are the reasons why: * Text-based content is more efficiently searchable than having to browse through images iteratively. * The rendering engine of HackMD can consistently generate well-structured layouts with annotated text instead of relying on arbitrary pictures. * It provides a more accessible and user-friendly experience for individuals with visual impairments. * Express what you have learned from [Chisel Bootcmap](https://github.com/sysprog21/chisel-bootcamp). * You should focus on how to improve `MyCPU` step by step, especially on how to overcome encountered issues, perform unit testing, ensure instruction set compatibility, and make sure that the software you develop can fully leverage the features of `MyCPU`. 6. BONUS: Enhance `MyCPU` to provide improved `ecall` and `break` support, along with [experimental system calls](https://github.com/sysprog21/rv32emu/blob/master/docs/syscall.md). This enhancement enables RISC-V programs to perform system calls similar to those supported in [rv32emu](https://github.com/sysprog21/rv32emu), demonstrating the capability of running applications such as Doom and Quake within `MyCPU`.