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tags: computer-arch
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# Assignment 1: RISC-V Assembly and Instruction Pipeline
> ==Due: Oct 13, 2025==

## Requirements
1. Following the instructions in [Lab1: RV32I Simulator](/@sysprog/H1TpVYMdB), get acquainted with RISC-V assembly programs ([RV32I](https://en.wikipedia.org/wiki/RISC-V) ISA) and output to the console using environment calls.
2. Complete Problems B and C from [Quiz 1](https://hackmd.io/@sysprog/arch2025-quiz1-sol) by translating them from C code into full RISC-V assembly programs, including relevant test data.
* Avoid a purely mechanical, line-by-line translation from C. Instead, demonstrate improvements in both code size and runtime performance beyond what a general C compiler would generate. Leverage the strengths of the RISC-V architecture for efficiency.
* Develop a simplified but informative use case to frame your assignment. You may select examples from [LeetCode](https://leetcode.com/) or practical open-source projects related to the quiz problems. For instance:
* *Implement log2 with branchless clz* ([bit hacks reference](https://graphics.stanford.edu/~seander/bithacks.html))
* *Matrix multiplication using bfloat16* ([Hugging Face blog](https://huggingface.co/blog/hf-bitsandbytes-integration))
* *Optimize LeetCode Problem #X using half-precision floating point to reduce memory usage*
* Use only **RV32I instructions** (without M or F/D extensions) for floating-point manipulation. You must write RISC-V assembly from scratch—do not rely on compiler-generated routines.
* Include at least **three test data cases**. Predefined data may be inlined directly. Automate testing wherever possible by including internal validation rather than manually checking outputs.
* Show iterative refinement of your assembly programs, including reducing code size and runtime overhead, with explicit measurements.
* While you must **write your own RISC-V assembly**, you may compare against compiler output for verification and discussion.
* Ensure that all programs run correctly on the [Ripes](https://github.com/mortbopet/Ripes) simulator.
* You MUST fork from [ca2025-quizzes](https://github.com/sysprog21/ca2025-quizzes) and push git commits with meaningful commit messages (see [How to Write a Git Commit Message](https://cbea.ms/git-commit/)). Ensure the repository you fork is public.
* References: [Example RISC-V Assembly Programs](https://marz.utk.edu/my-courses/cosc230/book/example-risc-v-assembly-programs/) and [arch-riscv-progs](https://github.com/sysprog21/arch-riscv-progs).
3. Provide explanations for both program functionality and instruction-level operations using the Ripes simulator.
* Use visualization of signals such as register write/enable, multiplexer selection, etc.
* Demonstrate each stage: IF, ID, IE, MEM, WB.
* Explain memory update steps and their correctness.
4. Document your progress in [HackMD notes](https://hackmd.io/s/features).
* See [example page](https://hackmd.io/@sysprog/SkkbXLJRR).
* Insert both HackMD notes and RISC-V assembly programs in the assignment table.
* Your HackMD page must be [Published](https://hackmd.io/s/all-about-profile-page) and editable as *Signed-in write*.
* **All writing must be in English.** You may use ChatGPT, [QuillBot](https://quillbot.com/), or similar AI tools to refine your writing, provided you comply with the [AI Guidelines for Computer Architecture (Fall 2025)](link-to-guidelines). Transparency and substantial personal contribution are required.
5. Fill in [Google Form](https://forms.gle/Voy3Q8wqPNRiegt66) to submit your work.
5. **BONUS:** Active participation in class discussions during code reviews or quiz reviews may earn extra credit.