---
# System prepended metadata

title: Lab 8_CS22B036

---

# Lab 8
Name: M V Sonith
Roll No.: CS22B036

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## Question 1
**Half adder Code**
```verilog=
module half_adder1(a,b,s,c);
    input a,b;
    output s,c;
    assign s = a^b;
    assign c = a&b;
endmodule
```
**Full adder Code**
```verilog=
module full_adder1(a,b,cin,s,cout);
    input a,b,cin;
    output s,cout;
    wire s1,c1,c0;
    half_adder1 h0(a,b,s1,c0);
    half_adder1 h1(s1,cin,s,c1);
    or(cout,c0,c1);
endmodule
```
**Test Bench Code**
```verilog=
module FA_TB();
    reg A,B,C;
    wire S,Cout;
    
    full_adder1 h01(.a(A),.b(B),.cin(C),.s(S),.cout(Cout));
    
    initial 
    begin
        $monitor("A=%b,B=%b,C=%b,S=%b,Cout=%b",A,B,C,S,Cout);
        A=1'b0;B=1'b0;C=1'b0;
        #100;
        A=1'b0;B=1'b0;C=1'b1;
        #100;
        A=1'b0;B=1'b1;C=1'b0;
        #100;
        A=1'b0;B=1'b1;C=1'b1;
        #100;
        A=1'b1;B=1'b0;C=1'b0;
        #100;
        A=1'b1;B=1'b0;C=1'b1;
        #100;
        A=1'b1;B=1'b1;C=1'b0;
        #100;
        A=1'b1;B=1'b1;C=1'b1;
    end
endmodule
```
**Output**
![Screenshot from 2024-03-26 17-02-03](https://hackmd.io/_uploads/rJvwBVekA.png)


---
## Question 2
**Ripple Adder Code**
```verilog=
module Nbit_adder(a1,b1,s1);
    input [3:0]a1;
    input [3:0]b1;
    output [4:0]s1;
    wire [4:0]c1;
    assign c1[0] = 1'b0;
    genvar i;
    generate
    for(i=0;i<4;i=i+1)
    begin
        full_adder1 DUT1(.a(a1[i]),.b(b1[i]),.cin(c1[i]),.s(s1[i]),.cout(c1[i+1]));
    end
    endgenerate
    assign s1[4] = c1[4];
    endmodule
```
**Test Bench Code**
```verilog=
module adderTB();
    reg [3:0] A;
    reg [3:0] B;
    wire [4:0] AS;
    Nbit_adder H0(.a1(A),.b1(B),.s1(AS));
    
    initial
    begin
        $monitor("A=%d,B=%d,S=%d",A,B,AS);
        A=4'b0000;B=4'b0001;
        #100;
        A=4'b0011;B=4'b0001;
        #100;
        A=4'b1111;B=4'b0001;
        #100;
        A=4'b0110;B=4'b1001;
    end
endmodule
```
**Output**
![Screenshot from 2024-03-26 17-09-20](https://hackmd.io/_uploads/rJaKHNlkA.png)


---
## Question 3
**Multiplexer Code**
```verilog=
module multiplexer(a0,a1,s,out1);
    input a0,a1,s;
    output out1;
    wire w1,w2,w3;
    not(w1,s);
    and(w2,w1,a0);
    and(w3,s,a1);
    or (out1,w2,w3);
endmodule
```
**Test Bench Code**
```verilog=
module MultiTB();
    reg b0,b1,s1;
    wire y;
    
    multiplexer M1(.a0(b0),.a1(b1),.s(s1),.out1(y));
    
    initial
    begin
         $monitor("a0=%b,a1=%b,s=%b,out=%b",b0,b1,s1,y);
        b0=1'b0;b1=1'b0;s1=1'b0;
        #100;
        b0=1'b0;b1=1'b0;s1=1'b1;
        #100;
        b0=1'b0;b1=1'b1;s1=1'b0;
        #100;
        b0=1'b0;b1=1'b1;s1=1'b1;
        #100;
        b0=1'b1;b1=1'b0;s1=1'b0;
        #100;
        b0=1'b1;b1=1'b0;s1=1'b1;
        #100;
        b0=1'b1;b1=1'b1;s1=1'b0;
        #100;
        b0=1'b1;b1=1'b1;s1=1'b1;
    end
endmodule
```
**Output**
![Screenshot from 2024-03-26 17-13-19](https://hackmd.io/_uploads/ryy2BNlJ0.png)



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