# Lab 10 , 11
Name: M V Sonith
Roll No.: CS22B036
---
## 32 bit Adder
```verilog=
module half_adder1(a,b,s,c);
input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule
module full_adder1(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s1,c1,c0;
half_adder1 h0(a,b,s1,c0);
half_adder1 h1(s1,cin,s,c1);
or(cout,c0,c1);
endmodule
module Nbit_adder(s1,a1,b1);
input [31:0]a1;
input [31:0]b1;
output [31:0]s1;
wire [32:0]c1;
assign c1[0] = 1'b0;
genvar i;
generate
for(i=0;i<32;i=i+1)
begin
full_adder1 DUT1(.a(a1[i]),.b(b1[i]),.cin(c1[i]),.s(s1[i]),.cout(c1[i+1]));
end
endgenerate
endmodule
```
## 32 bit subtractor
```verilog=
module half_subtractor(a,b,d,bo);
input a,b;
wire a13;
output d,bo;
xor g1(d,a,b);
not(a13,a);
and(bo,a13,b);
endmodule
module full_subtractor(a,b,bi,y,bo);
input a,b,bi;
output y,bo;
wire w1,w2,w3;
half_subtractor g1(a,b,w1,w2);
half_subtractor g2(w1,bi,y,w3);
or(bo,w2,w3);
endmodule
module nbitsubtractor(s,a,b);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
wire [n-1:0] c;
genvar i;
generate
for (i = 0 ;i<n ;i=i+1 )
begin: t
if (i==0) begin
half_subtractor f(a[0],b[0],s[0],c[0]);
end
else begin
full_subtractor f(a[i],b[i],c[i-1],s[i],c[i]);
end
end
endgenerate
endmodule
```
## 32 bitwise XOR
```verilog=
module nbitxor(s,a,b);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
genvar i;
generate
for(i=0;i<32;i=i+1)
begin
xor(s[i],a[i],b[i]);
end
endgenerate
endmodule
```
## 32 bitwise OR
```verilog=
module nbitor(s,a,b);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
genvar i;
generate
for(i=0;i<32;i=i+1)
begin
or(s[i],a[i],b[i]);
end
endgenerate
endmodule
```
## 32 bitwise AND
```verilog=
module nbitand(s,a,b);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
genvar i;
generate
for(i=0;i<32;i=i+1)
begin
and(s[i],a[i],b[i]);
end
endgenerate
endmodule
```
## Left shifter
```verilog=
module leftshifter (s,a,b);
input [31:0]a,b;
output [31:0]s;
assign s = a<<b;
endmodule
```
## Right shifter
```verilog=
module rightshifter (s,a,b);
input [31:0]a,b;
output [31:0]s;
assign s = a>>b;
endmodule
```
## Right Arithmetic shifter
```verilog=
module rightarthshifter (s,a,b);
input [31:0]a,b;
output [31:0]s;
assign s = a>>>b;
endmodule
```
## 32 bit unsigned Comparator
```verilog=
module unsignedcompu(s,a,b);
input [31:0] a,b;
output [31:0] s;
assign s = (a<b) ? 32'b1 : 32'b0;
endmodule
```
## 32 bit signed Comparator
```verilog=
module signedcompu(s,a,b);
input [31:0] a,b;
output [31:0] s;
assign s = ($signed(a) < $signed(b)) ? 32'b1 : 32'b0;
endmodule
```
## 2 to 1 mux
```verilog=
module muxt (a,b,sel,s);
input a,b;
input sel;
output s;
wire w11,w12,w13;
not(w11,sel);
and(w12,w11,a);
and(w13,sel,b);
or(s,w12,w13);
endmodule
```
## 4 to 1 mux
```verilog=
module muxf (a,a1,a2,a3,sel,s);
input a,a1,a2,a3;
input[1:0] sel;
output s;
wire w1, w2, w3;
muxt m11(a, a1, sel[0], w1);
muxt m12(a2, a3, sel[0], w2);
muxt m2(w1, w2, sel[1], w3);
assign s = w3;
endmodule
```
## 8 to 1 mux
```verilog=
module muxe (a,a1,a2,a3,a4,a5,a6,a7,sel,s);
input a,a1,a2,a3,a4,a5,a6,a7;
input[2:0] sel;
output s;
wire w1, w2, w3;
muxf m111(a,a1,a2,a3,sel[1:0], w1);
muxf m112(a4,a5,a6,a7,sel[1:0], w2);
muxt m21(w1, w2, sel[2], w3);
assign s = w3;
endmodule
```
## 16 to 1 mux
```verilog=
module muxsi (s,sel,a,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15);
input a,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15;
input[3:0] sel;
output s;
wire w1, w2, w3;
muxe m1111(a,a1,a2,a3,a4,a5,a6,a7,sel[2:0], w1);
muxe m1121(a8,a9,a10,a11,a12,a13,a14,a15,sel[2:0], w2);
muxt m211(w1, w2, sel[3], w3);
assign s = w3;
endmodule
```
## ALU
```verilog=
module ALU(a,b,s,op);
parameter n=32;
input [n-1:0] a,b;
output [n-1:0] s;
input [3:0] op;
wire[n-1:0] w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
Nbit_adder h01(w1,a,b);
nbitsubtractor h02(w2,a,b);
nbitxor h03(w3,a,b);
nbitor h04(w4,a,b);
nbitand h05(w5,a,b);
leftshifter h06(w6,a,b);
rightshifter h07(w7,a,b);
rightarthshifter h08(w8,a,b);
unsignedcompu h09(w9,a,b);
signedcompu h10(w10,a,b);
Nbit_adder h11(w11,a,b);
Nbit_adder h12(w12,a,b);
genvar i;
generate
for (i = 0;i<32 ;i=i+1 )
begin
muxsi h13(s[i],op,w1[i],w2[i],w3[i],w4[i],w5[i],w6[i],w7[i],w8[i],w9[i],w10[i],w11[i],w12[i],w13[i],w14[i],w15[i],w16[i]);
end
endgenerate
endmodule
```
## Data Memory File
```verilog=
module dataMemory(writeEnable,readEnable,address,writeData,readData,clk);
reg [31:0]mem[255:0];
input [31:0] address;
input [31:0] writeData;
input writeEnable,readEnable;
output reg [31:0] readData;
input clk;
always @(posedge clk)
begin
if (writeEnable)
begin
mem[address]=writeData;
end
if (readEnable)
begin
readData = mem[address];
end
end
endmodule
```
## Instruction Memory File
```verilog=
module insMemory(writeEnable,address,writeData,readData,clk);
reg [31:0]mem[255:0];
input [31:0] address;
input [31:0] writeData;
input writeEnable;
output reg [31:0] readData;
input clk;
initial
begin
mem[0] = 32'b00000000000100010000000110000001;
mem[1] = 32'b00000000000100010000001000000010;
end
always @(posedge clk)
begin
if (writeEnable)
begin
mem[address]=writeData;
end
readData = mem[address];
end
endmodule
```
## Register File
```verilog=
module registerFile(readEnable,rs1,rs2,rd,writeEnable,writeData,rsval1,rsval2,clk,opcode,immed);
reg [31:0]registers[31:0];
input [4:0]rs1,rs2,rd;
input [31:0]writeData;
input writeEnable,readEnable;
output reg [31:0]rsval1,rsval2;
input [3:0]opcode;
input [31:0]immed;
input clk;
initial
begin
registers[1]=32'b1;
registers[2]=32'b10;
end
always @(posedge clk)
begin
if (writeEnable)
begin
registers[rd]=writeData;
end
if (readEnable)
begin
rsval1=registers[rs1];
if (opcode==10)
begin
rsval2 = immed;
end
else if (opcode==11)
begin
rsval2 = immed;
end
else
begin
rsval2 = registers[rs2];
end
end
end
endmodule
```
## Decoder
```verilog=
module decoder(instruction,rs1,rs2,opcode,rd,immed,clk);
input [31:0]instruction ;
output reg[4:0]rs1,rs2,rd;
output reg[3:0]opcode;
output reg[31:0]immed;
input clk;
always @(posedge clk)
begin
opcode = instruction[3:0];
if (opcode==10)
begin
immed = {20'b00000000000000000000,instruction[31:20]};
rs1 = instruction[19:15];
rd = instruction[11:7];
end
else if (opcode==11)
begin
rs1 = instruction[19:15];
immed = {20'b00000000000000000000,instruction[31:25],instruction[11:7]};
rs2 = instruction[24:20];
end
else
begin
rs1 = instruction[19:15];
rs2 = instruction[24:20];
rd = instruction[11:7];
end
end
endmodule
```
## Processor
```verilog=
module Processor(clk);
input clk;
reg [31:0]pc;
wire [31:0]instruction;
reg we1,we2,we3,we4,re,re1,re2;
reg [31:0] wd;
wire [4:0]rs1,rs2,rd;
wire [31:0]immed;
wire [3:0]opcode;
wire [31:0]aluout;
wire [31:0]val1,val2,readMem,writeMem;
insMemory memi(we1,pc,wd,instruction,clk);
decoder dec(instruction,rs1,rs2,opcode,rd,immed,clk);
registerFile regf(re2,rs1,rs2,rd,we2,readMem,val1,val2,clk,opcode,immed);
ALU alu(val1,val2,aluout,opcode);
dataMemory rami(we3,re,aluout,readMem,writeMem,clk);
registerFile regf2(re1,rs1,rs2,rd,we4,readMem,val1,val2,clk,opcode,immed);
initial begin
pc = 32'b0;
end
always @(posedge clk )
begin
if (pc < 5)
begin
pc = pc+1;
we1 = 1'b0;
we2 = 1'b0;
re2 = 1'b1;
if (opcode==10)
begin
re = 1'b1;
we3 = 1'b0;
we4 = 1'b1;
re1 = 1'b0;
end
else if (opcode==11)
begin
re = 1'b0;
we3 = 1'b1;
we4 = 1'b0;
re1 = 1'b0;
end
else
begin
re = 1'b0;
we3 = 1'b0;
we4 = 1'b0;
re1 = 1'b1;
end
end
end
endmodule
```
## TestBench
```verilog=
module TB();
reg clk;
Processor p1(clk);
initial
begin
$dumpfile("alu.vcd");
$dumpvars(0,p1);
end
initial
begin
clk = 1'b0;
forever
begin
#5
clk = ~clk;
end
end
initial
begin
#200 $finish;
end
endmodule
```
## Output
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