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# System prepended metadata

title: Assignment 4

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# Assignment 4
Name: M V Sonith
Roll No.: CS22B036

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## Ternary Logic Operations

<div style="display: inline-block; width: 33%;">
    
### OR operation

| A        | B        | A+B   |
| -------- | -------- | -------- |
| 0  | 0  |  0  |
| 0  | 1  |  1  |
| 1  | 0  |  1  |
| 0  | 2  |  2  |
| 2  | 0  |  2  |
| 1  | 1  |  1  |
| 1  | 2  |  2  |
| 2  | 1  |  2  |
| 2  | 2  |  2  |
</div>
<div style="display: inline-block; width: 33%;">
    
### AND operation

| A  | B  | A.B   |
| -- | -- | -------- |
| 0  | 0  |  0  |
| 0  | 1  |  0  |
| 1  | 0  |  0  |
| 0  | 2  |  0  |
| 2  | 0  |  0  |
| 1  | 1  |  1  |
| 1  | 2  |  1  |
| 2  | 1  |  1  |
| 2  | 2  |  2  |
</div>
<div style="display: inline-block; width: 33%; vertical-align: top;">
    
### NOT operation

| A  | ~A  |
| ---|---- |
| 0  | 2  |
| 1  | 1  |
| 2  | 0  |
</div>

**From this basic operations we can obtain for XOR,NAND,NOR opreartion with same logic from binary logic operations**

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## Instruction Encoding

**27 trits for Instruction**
**27 trit 27 registers**

### R - Type
0 - 6 trits : opcode
7 - 10 trits: dest
11- 12 trits: func2
13 -16 trits: src1
17- 20 trits: src2
21- 26 trits: func6

### I - Type
0 - 6 trits : opcode
7 - 10 trits: dest
11- 12 trits: func2
13 -16 trits: src1
17 -26 trits: immediate[0:9]

### S - Type
0 - 6 trits : opcode
7 - 10 trits: immediate[0:3]
11- 12 trits: func2
13 -16 trits: src1
17- 20 trits: src2
21- 26 trits: immediate[4:9]

### SB - Type
0 - 6 trits : opcode
7 - 10 trits: immediate[1:3],immediate[9]
11- 12 trits: func2
13 -16 trits: src1
17- 20 trits: src2
21- 26 trits: immediate[4:8],immediate[10]

### J - Type
0 - 6 trits : opcode
7 - 10 trits: dest
11- 26 trits: immediate[8:14],immediate[7],immediate[1:6],immediate[15]

### UJ - Type
0 - 6 trits : opcode
7 - 10 trits: dest
11- 26 trits: immediate[12:26]


**I've selected an instruction encoding similar to RISC-V in binary to facilitate the implementation of the same architecture for a processor with minimal alterations.**


## Pipeline Architecture

The classic 5 stage pipeline will work fine because it has been in industry and been optimized over decades to give optimal performance.

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## Address Range and Capacity
The addressable range has been increase exponentially with ternary logic with same number of transistors as they are ternary.The memory has been increased without increase in physical memory compared to binary.

The access time may remains same as binary logic.

But we get edge over computing  as 3^n^ instead of 2^n^ , for floating point numbers we get higher precision than that of binary.

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## Memory Organization

### Memory

Memory can store more data than that of binary architechture.

### Cache
 we may use same cache organization that of Binary.
 
 For valid and dirty trits we fix 2 as valid as state as fixing more than one valid state as we may get false results and cause errors.
 
 We can store more data than that of binary which may decrease miss rate resulting in better performance.The increased memory size may also leverage it.


### Number of Levels of Cache

we can keep same number of cache levels or less as cache is more denser for ternary compared to the binary.










