# Meeting 19.12.2020

- Participants: Alexander Hacker, Selina Weber
- Topic: how to handle the data stream of the DEDRA sensors

### Requirements for the data handling
- 4 Sensors
- Each sensor provides 5 MHz of sampling data, each made of 10bits
- Max. 50 kB buffer for 2 ms of stored data

### Possible solutions/ideas
- Use the data line for time delay
- (Replace the microcontroller)
- Multiplexing the ADCs
- Use buffer and erase it after a certain time (data may be lost)
- Try some kind of filtering before converting the analog singal in a digital one
- Idea for the data bus: place the microcontrollers as near as possible to the sensors

### Open questions
- Which data bus can handle the 5 MHz rate? STM32 provides I2C, UART, SPI (...?)
- Is the STM32 fast enough to process the incoming data?
- Therefore, do we want to replace it?
- Can we use the concept of "Transientenrekorder" for this issue?

### Summary
- We want to avoid an external memory/buffer if possible

### Actions
- Research. Do a lot of research (especially how it was done in the past)
- Meet again in the next weeks (Alexander, Alza, Selina)
- Test if the STM32 is capable to do the task

# Meeting 31.12.2020
### Idea No. 1: Full digital
Analogue log-amped signal(s) -> ADC(s) -> Buffer IC(s) -> µC
- We store a fixed time of the signals in the Buffer IC(s)
- The µC takes e.g. every 100th input value by sending a read signal
- If the µC detects that a constant threshold is exceeded or the difference to the previous signal is higher than a threshold, it sends a signal to fully read the buffer.
- During the read process, no new data is written into the FIFO IC leading to a certain downtime (TBC, maybe it is possible to read and write at the same time)
- datasheet of a possible buffer IC: https://www.renesas.com/eu/en/document/dst/72v201-72v251-datasheet

### Idea No. 2: Analogue comparator
Analogue log-amped signal(s) -> Comparator -> ADC(s) (-> Buffer IC(s)) -> µC
- not the entire analogue signal is converted to digital but the stream is pre-filtered
- only if a (variable) threshold voltage on one comparator pins is exceeded, the signal progresses to the ADC(s)

### Idea No. 3: Analogue comparator, delay and differential amplifier
Two paths for two trigger modes (OR logic):
Constant threshold path:
Analogue log-amped signal(s) -> Comparator -> ADC(s) (-> Buffer IC(s)) -> µC
Transient trigger path:
Analogue log-amped signal(s) -> delay loop -> difference amplifier -> comparator -> ADC(s) (-> Buffer IC(s)) -> µC
- same functionality as Idea No. 2 but with an added "slope trigger"
- the signal is copied and delayed by a certain time
- the real-time and delayed version progress to a differential amplifier
- only if the difference between the delayed and the real-time signal exceeds a threshold, the signal is converted to digital

### Idea No. 4: Use only STM32L496... SoC as FEED
- use the internal ADCs of the µC (3ADCs x 6.15 MSamples/s @ 10bit)
- to facilitate 4 or 5 (deep sensor) channels, multiplexing can be used
- this would cut down the sampling rate by a factor of 2, ending up at 3.07 MSamples/s

### Way forward
start with Idea No. 4:
- program a simple script to check the feasibility of this solution
- use a arbitrary signal generator in pulse setting to supply a voltage in the ADC range to a RC network
- connect the ADC input and an oscilloscope to the RC-networks outlet and compare the results

→ Set up a meeting with Matti to discuss this idea and and a possible schedule

- @Selina & Alza prepare by reading some forum articles to find some potential limitations of the built-in ADCs (e.g. noise, voltage range etc)
- @Alex prepare a flowchart of a potential test setup and trigger logic

# Meeting 03.01.2020 w/ Matti
- Idea No. 4 could be feasible. A driver for the internal ADCs shall be started to verify the feasibility.
- If we find problems in the STM's capabilities, we can go to alternative No. 1 next w/ external ADC and FIFO IC
- maybe there is some potential for a bachelor thesis