# ICON Liskov Generation Targets

### Simple Stencil Case

**Fortran Stencil**

!$ACC PARALLEL IF( i_am_accel_node .AND. acc_on ) DEFAULT(NONE) ASYNC(1)
            !$ACC LOOP GANG VECTOR
            DO jk = 1, nlev
              DO jc = i_startidx_2, i_endidx_2
                z_rth_pr(jc,jk,1,1) = 0._wp
                z_rth_pr(jc,jk,1,2) = 0._wp
              ENDDO
            ENDDO
!$ACC END PARALLEL

- Fortran preprocessor needs to be aware of start and end of each "stencil". Markers can be set using preprocessor `start` and `end` directives.

**Call to DSL interface (gt4py)**

call wrap_run_mo_velocity_advection_stencil_07(
		vn_ie=p_diag%vn_ie(:,:,1), & 
        inv_dual_edge_length=p_patch%edges%inv_dual_edge_length(:,1), &  
        w=p_prog%w(:,:,1), z_vt_ie=z_vt_ie(:,:,1), &
        inv_primal_edge_length=p_patch%edges%inv_primal_edge_length(:,1), &
        tangent_orientation=p_patch%edges%tangent_orientation(:,1), &
        z_w_v=z_w_v(:,:,1), &
        z_v_grad_w=z_v_grad_w(:,:,1), z_v_grad_w_before=z_v_grad_w_before(:,:,1), &
        z_v_grad_w_abs_tol=1e-16_wp, &
        vertical_lower=1, &
        vertical_upper=nlev, &
        horizontal_lower=i_startidx, &
        horizontal_upper=i_endidx)

- Requires knowing name of target stencil.
- Requires knowing all arguments of stencil (in/out fields) as well as their dimensions.
- Requires knowledge of vertical and horizontal bounds, unless we pass these in from the gt4py stencil directly.
- Tolerances

**Nvtx profiling**

call nvtxStartRange("mo_solve_nonhydro_stencil_01")

! Fortran stencil code goes here

call nvtxEndRange()

- Requires knowing name of target stencil.

**Output field creation (copying)**

!$ACC PARALLEL IF( i_am_accel_node .AND. acc_on ) DEFAULT(NONE) ASYNC(1)
z_rth_pr_1_before(:,:,:) = z_rth_pr(:,:,:,1)
z_rth_pr_2_before(:,:,:) = z_rth_pr(:,:,:,2)
!$ACC END PARALLEL

- Requires names of output fields of the stencil.
- Needs to know dimensionality of each output field (unless a generic copy function can be written in Fortran to handle this).

**Importing DSL wrapped function interfaces**

USE mo_velocity_advection_stencil_01, ONLY: wrap_run_mo_velocity_advection_stencil_01

- Are these modules generated by `icon4pygen` at compile time?

**DSL in/out field declarations**

REAL(wp), DIMENSION(nproma,p_patch%nlev,p_patch%nblks_e) :: vt_before
REAL(wp), DIMENSION(nproma,p_patch%nlevp1,p_patch%nblks_e) :: vn_ie_before
REAL(wp), DIMENSION(nproma,p_patch%nlev,p_patch%nblks_e) :: z_kin_hor_e_before

- Requires configuring the different dimension variables for each field.

**Loading dsl fields onto the GPU**

!$ACC DATA COPYIN( z_w_concorr_me, z_kin_hor_e, z_vt_ie ), &

!$ACC CREATE(z_w_concorr_mc, z_w_con_c, cfl_clipping, z_w_con_c_full, z_v_grad_w, z_w_v, zeta, z_ekinh, levmask, levelmask, &

!$ACC vt_before, &

!$ACC vn_ie_before, z_kin_hor_e_before, &

!$ACC z_vt_ie_before, &

!$ACC z_w_concorr_me_before, &

!$ACC z_v_grad_w_before, &

!$ACC z_ekinh_before, &

!$ACC z_w_concorr_mc_before, &

!$ACC w_concorr_c_before, &

!$ACC z_w_con_c_before, &

!$ACC pre_levmask, &

!$ACC cfl_clipping_dsl, &

!$ACC pre_levelmask_dsl, &

!$ACC vcfl_dsl, &

!$ACC cfl_clipping_before, &

!$ACC pre_levelmask_before, &

!$ACC levelmask_dsl, &

!$ACC vcfl_before, &

!$ACC z_w_con_c_full_before, &

!$ACC ddt_w_adv_before, &

!$ACC ddt_vn_adv_before &

!$ACC ), &

!$ACC PRESENT( p_diag, p_prog, p_int, p_metrics, p_patch ), &

!$ACC PRESENT( iqidx, iqblk, ividx, icblk, icidx, ieidx, ieblk, incblk, ivblk, incidx ) &

!$ACC IF ( i_am_accel_node .AND. acc_on )

- Requires simple way of parsing ACC statements to be able to insert additional fields in `DATA CREATE` directive.

**General structure for a stencil**

The general structure of the generated code looks as follows for the simple stencil case:

#ifdef __DSL_VERIFY

<Output Field Creation>

<Nvtx Start>

<Fortran Stencil>

<Nvtx End>

#endif

<Call to DSL Interface>

### DSL Interface Call Generation

#### Simple case

- Stencil arguments input/output fields -> get them from parsed gt4py stencil.
- Horizontal and vertical bounds -> Either from DSL directive, or directly through `custom_domain` in gt4py.
- Name of target stencil -> get from gt4py stencil.
- `start` and `end` of Fortran stencil -> line numbers from DSL directives in file.