---
# System prepended metadata

title: CSAPP

---

# CSAPP

ch1
bus typically transfers a fixed chunk of bytes known as words.

ch2
1. 64-bit word size = give a virtual memory ranging from 0 to 2^64 - 1 bytes in computer.
2. if x = 0x01234567,

|               0x100| 0x101| 0x102|0X103
little endian =  67       54     32    10
Big endian    =  01       23     45    76

ch6 the memory hierarchy

## Principle of Locality(we pursue good locality or cache friendly)
1. good locality => lower miss rate
1. temporal locality = a memory location is referenced once, the same location will be likely to be referenced multiple time.
2. spatial locality = a memory location is referenced once, the nearby location's memory will be likely to be referenced in the future.


1. i-cache used for holding instructions. it is read-only and simpler.
2. d-cache used for holding program data.
3. unified cache for both instruction and data.
4. with separate i/d-cache, an instruction word and a data word can be read at the same time and no conflict missing occurs between them.
5. L1 i-cache, L1 d-cache, L2 unified cache, L3 unified cache

Impact
1. if memory size is larger, it will run slower
2. if block size is larger, it will transfer slower and miss penalty will increase.
...

1. Memory mountain = read throughput vs stride-k(arr + k) vs array size

ch8 virtual memory(VM)
1. virtual table can allow virtual address convert to physical address.
1. VM can allow 2 processes having two virtual page table, and mapping to the same physical memory location.
2. VM can simplify sharing,
3. simplify how to allocate memory to processes(no need to assign contiguous physical memory). for example, a process need k more contiguous memory, OS can assign k contiguous virtual memory pages mapping to arbitrary k physical memory pages

how MMU operate with other hardware
1. MMU is in CPU chip

~ for page hit
1. processor of CPU chip generate a virtual address and set to MMU
2. MMU parse it and kgenerate PTE address and request it from cache/main memory
3. cache/main memory returns the PTE to MMU
4. MMU parse the physical address and send it to cache/main memory
5. the cache/main memory returns data word to processor.

ch11
![](https://i.imgur.com/V5Ouu3k.png)


Ch12
They are shared between threads:
global variable
local static variable

In each thread, there is
local automatic variable


IO multiplexing
1. select(....) function can monitor different IO descriptor. 
2. It can wait/block until an IO event happen/descriptor ready and notify developers.


tlb and vipt meaning??
![](https://i.imgur.com/HuRWuZd.png)

CPU stall = the time taken for reading cache line is long so that CPU run out of things and waiting for the cache line.

https://en.wikipedia.org/wiki/CPU_cache

A 2-way associative cache (Piledriver’s L1 is 2-way) means that each main memory block can map to one of two cache blocks.


