Study Journal for SOC Design Course === About --- - [About](https://hackmd.io/@ruei7916/ry0oVreya) Notes --- [block-level I/O protocol](/nagPIc1_Q6edNQIfpeWeqw) [Wishbone bus](/fikoWEUlQ2WlzrQOOvAziQ) [Linker Script](/0bvCZ9TxSMinuXKua303Sw) Guides --- - [使用WSL建立實驗環境](https://hackmd.io/@ruei7916/B19OM4rK6) - [工具](/-ozjIMKKRP-Tt3VryaPpjw) Labs --- - [lab report](https://github.com/ruei7916/SOC-Design/tree/main/lab%20report) - [lab3](https://github.com/ruei7916/SOC-Design/tree/main/lab3) - [lab4-1](https://github.com/816-allen/SOC-Design-Lab4-1) - [lab4-2](https://github.com/816-allen/SOC-Design-Lab4-2) - [lab6](https://github.com/ruei7916/soc_design-lab6) - [lab-sdram](https://github.com/ruei7916/SOC_lab-sdram) - [final-project](https://github.com/ruei7916/SOC-final-project) Troubleshooting --- - [[vitis_hls] Top function not found when doing synthesis](https://hackmd.io/ZW9levpsQ2-twD9htSwyvg) - [[Caravel_soc] Error: unrecognized opcode, extension 'zicsr' required](https://hackmd.io/@ruei7916/HkVxDnadp) - [[vivado] WARNING: Converted tricell instance to logic](/qdM-vjEER3aBh0F8CPbUKQ)
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