---
# System prepended metadata

title: 工具
tags: [Tools, SOC]

---

# 工具
工欲善其事，必先利其器
## VS Code and extensions ![image alt](https://code.visualstudio.com/assets/images/code-stable.png =10%x)(https://code.visualstudio.com/)
### verilog
- Verilog-HDL/SystemVerilog/Bluespec SystemVerilog **+ iverilog + ctags**
  ![圖片](https://hackmd.io/_uploads/r1lPKkwtT.png)
  安裝完iverilog跟ctags後要到Settings中設定
  `verilog.linting.linter`
  `verilog.ctags.path`
- Verilog Snippet
![圖片](https://hackmd.io/_uploads/Hkk_tJvFT.png)

  #### 參考:
  - https://zhuanlan.zhihu.com/p/95081329
  - https://zhuanlan.zhihu.com/p/338497672
### risc-v assembly
- ![圖片](https://hackmd.io/_uploads/B1XcY1vFT.png)

### C/C++
- ![圖片](https://hackmd.io/_uploads/Bk1l9ywtp.png)


### linker script
- ![圖片](https://hackmd.io/_uploads/r1E-FyvK6.png)


### general
- indent-rainbow
  ![圖片](https://hackmd.io/_uploads/BJJz5ywYp.png)
  ![圖片](https://hackmd.io/_uploads/H1f1i1DYp.png)


## WaveDrom(https://wavedrom.com)
- a Free and Open Source tool for drawing digital timing diagram (waveform)
- ![圖片](https://hackmd.io/_uploads/SJpHwkvFT.png)
