# 工具
工欲善其事，必先利其器
## VS Code and extensions (https://code.visualstudio.com/)
### verilog
- Verilog-HDL/SystemVerilog/Bluespec SystemVerilog **+ iverilog + ctags**
安裝完iverilog跟ctags後要到Settings中設定
`verilog.linting.linter`
`verilog.ctags.path`
- Verilog Snippet

#### 參考:
- https://zhuanlan.zhihu.com/p/95081329
- https://zhuanlan.zhihu.com/p/338497672
### risc-v assembly
- 

### C/C++
- 

### linker script
- 

### general
- indent-rainbow

## WaveDrom(https://wavedrom.com)
- a Free and Open Source tool for drawing digital timing diagram (waveform)
-