# [Caravel_SoC] Error: unrecognized opcode, extension 'zicsr' required
## Problem
The error message appears while compiling firmware code.

Error: unrecognized opcode `csrw mtvec,a0', extension `zicsr' required

## Solution
Modified the compiler architecture flag from `-march=rv32i` to `-march=rv32i_zicsr` to work with modern GCC.
### Reference:
- [Updated compiler target architecture](https://github.com/efabless/caravel_board/pull/86)
- [Recent versions of RISC-V gcc require "zicsr" in the compile line.](https://github.com/efabless/caravel_board/issues/87)
- [risc-v toolchain requirement should be documented](https://github.com/efabless/caravel_board/issues/37)
- [RISC-V GNU toolchain bumping default ISA spec to 20191213](https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4)