# Wishbone bus ## Brief introduction - The Wishbone Bus is an **open source** hardware computer bus. - The aim is to allow the connection of differing cores to each other inside of a chip. - Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels. - The Wishbone Bus is used by many designs in the OpenCores project. ## Minimum Set of Control Signals Master: CLK_I, RST_I, CYC_O, STB_O, ACK_I Slave: CLK_I, RST_I, CYC_I, STB_I, ACK_O Address / Data ## signals ![1024px-Wishbone_Interface.svg](https://hackmd.io/_uploads/SyjJP_HYp.png) (slave side) RST_I: receives the reset output signal [RST_O] from the SYSCON. CLK_I: receives the clock output signal [CLK_O] from the SYSCON. ADR_I: receives the address from MASTER DAT_I: receives the data DAT_O: drives the data WE_I: READ(negate), WRITE(assert) STB_I: Valid data transfer cycle(kind of chip select) ACK_O: Acknowledge – the termination of a bus cycle (by slave) CYC_I: Bus Cycle in progress (active high) SEL_I: Valid data, i.e. Byte-enable ---- TGA: Address Tag, e.g. address size, protect. TGC: Cycle Tag, e.g. interrupt acknowledge, cache, single/block/RMW TGD_IO: Data tag type, e.g. parity, time stamp … Others: LOCK, RTY, SEL ### Reference [Wishbone Version B4](https://cdn.opencores.org/downloads/wbspec_b4.pdf) - PDF specification of latest version of Wishbone